1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
9 #include <linux/mbus.h>
11 #include <asm/pl310.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
16 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
17 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
19 static struct mbus_win windows[] = {
21 { MBUS_SPI_BASE, MBUS_SPI_SIZE,
22 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
25 { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
26 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
28 #ifdef CONFIG_ARMADA_MSYS
30 { MBUS_DFX_BASE, MBUS_DFX_SIZE, CPU_TARGET_DFX, 0 },
34 void lowlevel_init(void)
37 * Dummy implementation, we only need LOWLEVEL_INIT
38 * on Armada to configure CP15 in start.S / cpu_init_cp15()
42 void reset_cpu(unsigned long ignored)
44 struct mvebu_system_registers *reg =
45 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
47 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask);
48 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst);
53 int mvebu_soc_family(void)
55 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
64 return MVEBU_SOC_A375;
69 return MVEBU_SOC_A38X;
74 return MVEBU_SOC_MSYS;
77 return MVEBU_SOC_UNKNOWN;
80 #if defined(CONFIG_DISPLAY_CPUINFO)
82 #if defined(CONFIG_ARMADA_375)
83 /* SAR frequency values for Armada 375 */
84 static const struct sar_freq_modes sar_freq_tab[] = {
85 { 0, 0x0, 266, 133, 266 },
86 { 1, 0x0, 333, 167, 167 },
87 { 2, 0x0, 333, 167, 222 },
88 { 3, 0x0, 333, 167, 333 },
89 { 4, 0x0, 400, 200, 200 },
90 { 5, 0x0, 400, 200, 267 },
91 { 6, 0x0, 400, 200, 400 },
92 { 7, 0x0, 500, 250, 250 },
93 { 8, 0x0, 500, 250, 334 },
94 { 9, 0x0, 500, 250, 500 },
95 { 10, 0x0, 533, 267, 267 },
96 { 11, 0x0, 533, 267, 356 },
97 { 12, 0x0, 533, 267, 533 },
98 { 13, 0x0, 600, 300, 300 },
99 { 14, 0x0, 600, 300, 400 },
100 { 15, 0x0, 600, 300, 600 },
101 { 16, 0x0, 666, 333, 333 },
102 { 17, 0x0, 666, 333, 444 },
103 { 18, 0x0, 666, 333, 666 },
104 { 19, 0x0, 800, 400, 267 },
105 { 20, 0x0, 800, 400, 400 },
106 { 21, 0x0, 800, 400, 534 },
107 { 22, 0x0, 900, 450, 300 },
108 { 23, 0x0, 900, 450, 450 },
109 { 24, 0x0, 900, 450, 600 },
110 { 25, 0x0, 1000, 500, 500 },
111 { 26, 0x0, 1000, 500, 667 },
112 { 27, 0x0, 1000, 333, 500 },
113 { 28, 0x0, 400, 400, 400 },
114 { 29, 0x0, 1100, 550, 550 },
115 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
117 #elif defined(CONFIG_ARMADA_38X)
118 /* SAR frequency values for Armada 38x */
119 static const struct sar_freq_modes sar_freq_tab[] = {
120 { 0x0, 0x0, 666, 333, 333 },
121 { 0x2, 0x0, 800, 400, 400 },
122 { 0x4, 0x0, 1066, 533, 533 },
123 { 0x6, 0x0, 1200, 600, 600 },
124 { 0x8, 0x0, 1332, 666, 666 },
125 { 0xc, 0x0, 1600, 800, 800 },
126 { 0x10, 0x0, 1866, 933, 933 },
127 { 0x13, 0x0, 2000, 1000, 933 },
128 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
130 #elif defined(CONFIG_ARMADA_MSYS)
131 static const struct sar_freq_modes sar_freq_tab[] = {
132 { 0x0, 0x0, 400, 400, 400 },
133 { 0x2, 0x0, 667, 333, 667 },
134 { 0x3, 0x0, 800, 400, 800 },
135 { 0x5, 0x0, 800, 400, 800 },
136 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
139 /* SAR frequency values for Armada XP */
140 static const struct sar_freq_modes sar_freq_tab[] = {
141 { 0xa, 0x5, 800, 400, 400 },
142 { 0x1, 0x5, 1066, 533, 533 },
143 { 0x2, 0x5, 1200, 600, 600 },
144 { 0x2, 0x9, 1200, 600, 400 },
145 { 0x3, 0x5, 1333, 667, 667 },
146 { 0x4, 0x5, 1500, 750, 750 },
147 { 0x4, 0x9, 1500, 750, 500 },
148 { 0xb, 0x9, 1600, 800, 533 },
149 { 0xb, 0xa, 1600, 800, 640 },
150 { 0xb, 0x5, 1600, 800, 800 },
151 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
155 void get_sar_freq(struct sar_freq_modes *sar_freq)
161 #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
162 val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
164 val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
166 freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
167 #if defined(SAR2_CPU_FREQ_MASK)
169 * Shift CPU0 clock frequency select bit from SAR2 register
170 * into correct position
172 freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
173 >> SAR2_CPU_FREQ_OFFS) << 3;
175 for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
176 if (sar_freq_tab[i].val == freq) {
177 #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
178 *sar_freq = sar_freq_tab[i];
184 ffc = (val & SAR_FFC_FREQ_MASK) >>
186 for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
187 if (sar_freq_tab[k].ffc == ffc) {
188 *sar_freq = sar_freq_tab[k];
197 /* SAR value not found, return 0 for frequencies */
198 *sar_freq = sar_freq_tab[i - 1];
201 int print_cpuinfo(void)
203 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
204 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
205 struct sar_freq_modes sar_freq;
231 case SOC_98DX3236_ID:
234 case SOC_98DX3336_ID:
237 case SOC_98DX4251_ID:
245 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
254 printf("?? (%x)", revid);
259 if (mvebu_soc_family() == MVEBU_SOC_A375) {
261 case MV_88F67XX_A0_ID:
265 printf("?? (%x)", revid);
270 if (mvebu_soc_family() == MVEBU_SOC_A38X) {
272 case MV_88F68XX_Z1_ID:
275 case MV_88F68XX_A0_ID:
278 case MV_88F68XX_B0_ID:
282 printf("?? (%x)", revid);
287 if (mvebu_soc_family() == MVEBU_SOC_MSYS) {
296 printf("?? (%x)", revid);
301 get_sar_freq(&sar_freq);
302 printf(" at %d MHz\n", sar_freq.p_clk);
306 #endif /* CONFIG_DISPLAY_CPUINFO */
309 * This function initialize Controller DRAM Fastpath windows.
310 * It takes the CS size information from the 0x1500 scratch registers
311 * and sets the correct windows sizes and base addresses accordingly.
313 * These values are set in the scratch registers by the Marvell
314 * DDR3 training code, which is executed by the SPL before the
315 * main payload (U-Boot) is executed.
317 static void update_sdram_window_sizes(void)
323 for (i = 0; i < SDRAM_MAX_CS; i++) {
324 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
326 size |= ~(SDRAM_ADDR_MASK);
328 /* Set Base Address */
329 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
330 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
333 * Check if out of max window size and resize
336 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
337 ~(SDRAM_ADDR_MASK)) | 1;
338 temp |= (size & SDRAM_ADDR_MASK);
339 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
341 base += ((u64)size + 1);
344 * Disable window if not used, otherwise this
345 * leads to overlapping enabled windows with
346 * pretty strange results
348 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
353 void mmu_disable(void)
356 "mrc p15, 0, r0, c1, c0, 0\n"
358 "mcr p15, 0, r0, c1, c0, 0\n");
361 #ifdef CONFIG_ARCH_CPU_INIT
362 static void set_cbar(u32 addr)
364 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
367 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
368 #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
369 #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \
370 (((addr) & 0xF) << 6))
371 #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \
372 (((reg) & 0xF) << 2))
374 static void setup_usb_phys(void)
382 /* Setup PLL frequency */
383 /* USB REF frequency = 25 MHz */
384 clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
386 /* Power up PLL and PHY channel */
387 setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
389 /* Assert VCOCAL_START */
390 setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
395 * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
398 for (dev = 0; dev < 3; dev++) {
399 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
401 /* Assert REG_RCAL_START in channel REG 1 */
402 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
404 clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
409 * This function is not called from the SPL U-Boot version
411 int arch_cpu_init(void)
413 struct pl310_regs *const pl310 =
414 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
417 * Only with disabled MMU its possible to switch the base
418 * register address on Armada 38x. Without this the SDRAM
419 * located at >= 0x4000.0000 is also not accessible, as its
420 * still locked to cache.
424 /* Linux expects the internal registers to be at 0xf1000000 */
425 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
426 set_cbar(SOC_REGS_PHY_BASE + 0xC000);
429 * From this stage on, the SoC detection is working. As we have
430 * configured the internal register base to the value used
431 * in the macros / defines in the U-Boot header (soc.h).
434 if (mvebu_soc_family() == MVEBU_SOC_A38X) {
436 * To fully release / unlock this area from cache, we need
437 * to flush all caches and disable the L2 cache.
441 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
445 * We need to call mvebu_mbus_probe() before calling
446 * update_sdram_window_sizes() as it disables all previously
447 * configured mbus windows and then configures them as
448 * required for U-Boot. Calling update_sdram_window_sizes()
449 * without this configuration will not work, as the internal
450 * registers can't be accessed reliably because of potenial
452 * After updating the SDRAM access windows we need to call
453 * mvebu_mbus_probe() again, as this now correctly configures
454 * the SDRAM areas that are later used by the MVEBU drivers
459 * First disable all windows
461 mvebu_mbus_probe(NULL, 0);
463 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
465 * Now the SDRAM access windows can be reconfigured using
466 * the information in the SDRAM scratch pad registers
468 update_sdram_window_sizes();
472 * Finally the mbus windows can be configured with the
473 * updated SDRAM sizes
475 mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
477 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
478 /* Enable GBE0, GBE1, LCD and NFC PUP */
479 clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
480 GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
481 NAND_PUP_EN | SPI_PUP_EN);
483 /* Configure USB PLL and PHYs on AXP */
487 /* Enable NAND and NAND arbiter */
488 clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
490 /* Disable MBUS error propagation */
491 clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
495 #endif /* CONFIG_ARCH_CPU_INIT */
497 u32 mvebu_get_nand_clock(void)
501 if (mvebu_soc_family() == MVEBU_SOC_A38X)
502 reg = MVEBU_DFX_DIV_CLK_CTRL(1);
503 else if (mvebu_soc_family() == MVEBU_SOC_MSYS)
504 reg = MVEBU_DFX_DIV_CLK_CTRL(8);
506 reg = MVEBU_CORE_DIV_CLK_CTRL(1);
508 return CONFIG_SYS_MVEBU_PLL_CLOCK /
510 NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
514 * SOC specific misc init
516 #if defined(CONFIG_ARCH_MISC_INIT)
517 int arch_misc_init(void)
519 /* Nothing yet, perhaps we need something here later */
522 #endif /* CONFIG_ARCH_MISC_INIT */
524 #if defined(CONFIG_MMC_SDHCI_MV) && !defined(CONFIG_DM_MMC)
525 int board_mmc_init(bd_t *bis)
527 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
528 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
534 #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
535 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
537 #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
538 #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
539 #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
541 static void ahci_mvebu_mbus_config(void __iomem *base)
543 const struct mbus_dram_target_info *dram;
546 /* mbus is not initialized in SPL; keep the ROM settings */
547 if (IS_ENABLED(CONFIG_SPL_BUILD))
550 dram = mvebu_mbus_dram_info();
552 for (i = 0; i < 4; i++) {
553 writel(0, base + AHCI_WINDOW_CTRL(i));
554 writel(0, base + AHCI_WINDOW_BASE(i));
555 writel(0, base + AHCI_WINDOW_SIZE(i));
558 for (i = 0; i < dram->num_cs; i++) {
559 const struct mbus_dram_window *cs = dram->cs + i;
561 writel((cs->mbus_attr << 8) |
562 (dram->mbus_dram_target_id << 4) | 1,
563 base + AHCI_WINDOW_CTRL(i));
564 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
565 writel(((cs->size - 1) & 0xffff0000),
566 base + AHCI_WINDOW_SIZE(i));
570 static void ahci_mvebu_regret_option(void __iomem *base)
573 * Enable the regret bit to allow the SATA unit to regret a
574 * request that didn't receive an acknowlegde and avoid a
577 writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
578 writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
581 int board_ahci_enable(void)
583 ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
584 ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
589 #ifdef CONFIG_SCSI_AHCI_PLAT
592 printf("MVEBU SATA INIT\n");
594 ahci_init((void __iomem *)MVEBU_SATA0_BASE);
598 #ifdef CONFIG_USB_XHCI_MVEBU
599 #define USB3_MAX_WINDOWS 4
600 #define USB3_WIN_CTRL(w) (0x0 + ((w) * 8))
601 #define USB3_WIN_BASE(w) (0x4 + ((w) * 8))
603 static void xhci_mvebu_mbus_config(void __iomem *base,
604 const struct mbus_dram_target_info *dram)
608 for (i = 0; i < USB3_MAX_WINDOWS; i++) {
609 writel(0, base + USB3_WIN_CTRL(i));
610 writel(0, base + USB3_WIN_BASE(i));
613 for (i = 0; i < dram->num_cs; i++) {
614 const struct mbus_dram_window *cs = dram->cs + i;
616 /* Write size, attributes and target id to control register */
617 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
618 (dram->mbus_dram_target_id << 4) | 1,
619 base + USB3_WIN_CTRL(i));
621 /* Write base address to base register */
622 writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(i));
626 int board_xhci_enable(fdt_addr_t base)
628 const struct mbus_dram_target_info *dram;
630 printf("MVEBU XHCI INIT controller @ 0x%lx\n", base);
632 dram = mvebu_mbus_dram_info();
633 xhci_mvebu_mbus_config((void __iomem *)base, dram);
639 void enable_caches(void)
641 /* Avoid problem with e.g. neta ethernet driver */
642 invalidate_dcache_all();
645 * Armada 375 still has some problems with d-cache enabled in the
646 * ethernet driver (mvpp2). So lets keep the d-cache disabled
647 * until this is solved.
649 if (mvebu_soc_family() != MVEBU_SOC_A375) {
650 /* Enable D-cache. I-cache is already enabled in start.S */
655 void v7_outer_cache_enable(void)
657 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
658 struct pl310_regs *const pl310 =
659 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
662 /* The L2 cache is already disabled at this point */
665 * For Aurora cache in no outer mode, enable via the CP15
666 * coprocessor broadcasting of cache commands to L2.
668 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
669 u |= BIT(8); /* Set the FW bit */
670 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
674 /* Enable the L2 cache */
675 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
679 void v7_outer_cache_disable(void)
681 struct pl310_regs *const pl310 =
682 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
684 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);