1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
9 #include <linux/libfdt.h>
10 #include <linux/sizes.h>
13 #include <asm/system.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/soc.h>
16 #include <asm/armv8/mmu.h>
18 DECLARE_GLOBAL_DATA_PTR;
21 * Not all memory is mapped in the MMU. So we need to restrict the
22 * memory size so that U-Boot does not try to access it. Also, the
23 * internal registers are located at 0xf000.0000 - 0xffff.ffff.
24 * Currently only 2GiB are mapped for system memory. This is what
25 * we pass to the U-Boot subsystem here.
27 #define USABLE_RAM_SIZE 0x80000000
29 ulong board_get_usable_ram_top(ulong total_size)
31 if (gd->ram_size > USABLE_RAM_SIZE)
32 return USABLE_RAM_SIZE;
38 * On ARMv8, MBus is not configured in U-Boot. To enable compilation
39 * of the already implemented drivers, lets add a dummy version of
40 * this function so that linking does not fail.
42 const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
47 /* DRAM init code ... */
49 #define MV_SIP_DRAM_SIZE 0x82000010
51 static u64 a8k_dram_scan_ap_sz(void)
55 pregs.regs[0] = MV_SIP_DRAM_SIZE;
56 pregs.regs[1] = SOC_REGS_PHY_BASE;
62 static void a8k_dram_init_banksize(void)
65 * The firmware (ATF) leaves a 1G whole above the 3G mark for IO
66 * devices. Higher RAM is mapped at 4G.
68 * Config 2 DRAM banks:
69 * Bank 0 - max size 4G - 1G
70 * Bank 1 - ram size - 4G + 1G
72 phys_size_t max_bank0_size = SZ_4G - SZ_1G;
74 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
75 if (gd->ram_size <= max_bank0_size) {
76 gd->bd->bi_dram[0].size = gd->ram_size;
80 gd->bd->bi_dram[0].size = max_bank0_size;
81 if (CONFIG_NR_DRAM_BANKS > 1) {
82 gd->bd->bi_dram[1].start = SZ_4G;
83 gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size;
87 __weak int dram_init_banksize(void)
89 if (CONFIG_IS_ENABLED(ARMADA_8K))
90 a8k_dram_init_banksize();
92 fdtdec_setup_memory_banksize();
97 __weak int dram_init(void)
99 if (CONFIG_IS_ENABLED(ARMADA_8K)) {
100 gd->ram_size = a8k_dram_scan_ap_sz();
101 if (gd->ram_size != 0)
105 if (fdtdec_setup_mem_size_base() != 0)
111 int arch_cpu_init(void)
113 /* Nothing to do (yet) */
117 int arch_early_init_r(void)
124 * Loop over all MISC uclass drivers to call the comphy code
125 * and init all CP110 devices enabled in the DT
129 /* Call the comphy code via the MISC uclass driver */
130 ret = uclass_get_device(UCLASS_MISC, i++, &dev);
132 /* We're done, once no further CP110 device is found */
137 /* Cause the SATA device to do its early init */
138 uclass_first_device(UCLASS_AHCI, &dev);
141 /* Trigger PCIe devices detection */