1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
10 #include <asm/arch/gx.h>
11 #include <asm/arch/eth.h>
14 /* Configure the Ethernet MAC with the requested interface mode
15 * with some optional flags.
17 void meson_gx_eth_init(phy_interface_t mode, unsigned int flags)
20 case PHY_INTERFACE_MODE_RGMII:
21 case PHY_INTERFACE_MODE_RGMII_ID:
22 case PHY_INTERFACE_MODE_RGMII_RXID:
23 case PHY_INTERFACE_MODE_RGMII_TXID:
25 setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
26 GX_ETH_REG_0_TX_PHASE(1) |
27 GX_ETH_REG_0_TX_RATIO(4) |
28 GX_ETH_REG_0_PHY_CLK_EN |
32 case PHY_INTERFACE_MODE_RMII:
34 out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
37 /* Use GXL RMII Internal PHY */
38 if (IS_ENABLED(CONFIG_MESON_GXL) &&
39 (flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) {
40 writel(0x10110181, GX_ETH_REG_2);
41 writel(0xe40908ff, GX_ETH_REG_3);
47 printf("Invalid Ethernet interface mode\n");
51 /* Enable power and clock gate */
52 setbits_le32(GX_GCLK_MPEG_1, GX_GCLK_MPEG_1_ETH);
53 clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);