1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
4 * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
8 #include <asm/arch/boot.h>
9 #include <asm/arch/eth.h>
10 #include <asm/arch/axg.h>
11 #include <asm/arch/mem.h>
13 #include <asm/armv8/mmu.h>
14 #include <linux/sizes.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 int meson_get_boot_device(void)
21 return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
24 /* Configure the reserved memory zones exported by the secure registers
25 * into EFI and DTB reserved memory entries.
27 void meson_init_reserved_memory(void *fdt)
29 u64 bl31_size, bl31_start;
30 u64 bl32_size, bl32_start;
34 * Get ARM Trusted Firmware reserved memory zones in :
35 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
36 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
37 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
39 reg = readl(AXG_AO_SEC_GP_CFG3);
41 bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
42 >> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
43 bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
45 bl31_start = readl(AXG_AO_SEC_GP_CFG5);
46 bl32_start = readl(AXG_AO_SEC_GP_CFG4);
48 /* Add BL31 reserved zone */
49 if (bl31_start && bl31_size)
50 meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
52 /* Add BL32 reserved zone */
53 if (bl32_start && bl32_size)
54 meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
57 phys_size_t get_effective_memsize(void)
59 /* Size is reported in MiB, convert it in bytes */
60 return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
61 >> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
64 static struct mm_region axg_mem_map[] = {
69 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
75 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
77 PTE_BLOCK_PXN | PTE_BLOCK_UXN
84 struct mm_region *mem_map = axg_mem_map;
86 /* Configure the Ethernet MAC with the requested interface mode
87 * with some optional flags.
89 void meson_eth_init(phy_interface_t mode, unsigned int flags)
92 case PHY_INTERFACE_MODE_RGMII:
93 case PHY_INTERFACE_MODE_RGMII_ID:
94 case PHY_INTERFACE_MODE_RGMII_RXID:
95 case PHY_INTERFACE_MODE_RGMII_TXID:
97 setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
98 AXG_ETH_REG_0_TX_PHASE(1) |
99 AXG_ETH_REG_0_TX_RATIO(4) |
100 AXG_ETH_REG_0_PHY_CLK_EN |
101 AXG_ETH_REG_0_CLK_EN);
104 case PHY_INTERFACE_MODE_RMII:
106 out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
107 AXG_ETH_REG_0_INVERT_RMII_CLK |
108 AXG_ETH_REG_0_CLK_EN);
112 printf("Invalid Ethernet interface mode\n");
116 /* Enable power gate */
117 clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);