arch/arm/mach-mediatek/mt8516/init.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 MediaTek Inc.
   4  * Copyright (C) 2019 BayLibre, SAS
   5  * Author: Fabien Parent <fparent@baylibre.com>
   6  */
   7
   8 #include <clk.h>
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <dm.h>
  12 #include <fdtdec.h>
  13 #include <ram.h>
  14 #include <asm/arch/misc.h>
  15 #include <asm/armv8/mmu.h>
  16 #include <asm/sections.h>
  17 #include <dm/uclass.h>
  18 #include <dt-bindings/clock/mt8516-clk.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 int dram_init(void)
  23 {
  24         int ret;
  25
  26         ret = fdtdec_setup_memory_banksize();
  27         if (ret)
  28                 return ret;
  29
  30         return fdtdec_setup_mem_size_base();
  31 }
  32
  33 int dram_init_banksize(void)
  34 {
  35         gd->bd->bi_dram[0].start = gd->ram_base;
  36         gd->bd->bi_dram[0].size = gd->ram_size;
  37
  38         return 0;
  39 }
  40
  41 int mtk_pll_early_init(void)
  42 {
  43         unsigned long pll_rates[] = {
  44                 [CLK_APMIXED_ARMPLL] =   1300000000,
  45                 [CLK_APMIXED_MAINPLL] =  1501000000,
  46                 [CLK_APMIXED_UNIVPLL] =  1248000000,
  47                 [CLK_APMIXED_MMPLL] =     380000000,
  48         };
  49         struct udevice *dev;
  50         int ret, i;
  51
  52         ret = uclass_get_device_by_driver(UCLASS_CLK,
  53                         DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
  54         if (ret)
  55                 return ret;
  56
  57         /* configure default rate then enable apmixedsys */
  58         for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
  59                 struct clk clk = { .id = i, .dev = dev };
  60
  61                 ret = clk_set_rate(&clk, pll_rates[i]);
  62                 if (ret)
  63                         return ret;
  64
  65                 ret = clk_enable(&clk);
  66                 if (ret)
  67                         return ret;
  68         }
  69
  70         return 0;
  71 }
  72
  73 int mtk_soc_early_init(void)
  74 {
  75         int ret;
  76
  77         /* initialize early clocks */
  78         ret = mtk_pll_early_init();
  79         if (ret)
  80                 return ret;
  81
  82         return 0;
  83 }
  84
  85 void reset_cpu(ulong addr)
  86 {
  87         psci_system_reset();
  88 }
  89
  90 int print_cpuinfo(void)
  91 {
  92         printf("CPU:   MediaTek MT8516\n");
  93         return 0;
  94 }
  95
  96 static struct mm_region mt8516_mem_map[] = {
  97         {
  98                 /* DDR */
  99                 .virt = 0x40000000UL,
 100                 .phys = 0x40000000UL,
 101                 .size = 0x20000000UL,
 102                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
 103         }, {
 104                 .virt = 0x00000000UL,
 105                 .phys = 0x00000000UL,
 106                 .size = 0x20000000UL,
 107                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 108                          PTE_BLOCK_NON_SHARE |
 109                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 110         }, {
 111                 0,
 112         }
 113 };
 114 struct mm_region *mem_map = mt8516_mem_map;