1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Lei Wen <leiwen@marvell.com>
9 * This file should be included in board config header file.
11 * It supports common definitions for Kirkwood platform
17 #if defined (CONFIG_KW88F6281)
18 #include <asm/arch/kw88f6281.h>
19 #elif defined (CONFIG_KW88F6192)
20 #include <asm/arch/kw88f6192.h>
22 #error "SOC Name not defined"
23 #endif /* CONFIG_KW88F6281 */
25 #include <asm/arch/soc.h>
26 #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
27 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
28 #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
30 * Disable the dcache. Currently the network driver (mvgbe.c) and USB
31 * EHCI driver (ehci-marvell.c) and possibly others rely on the data
32 * cache being disabled.
34 #define CONFIG_SYS_DCACHE_OFF
37 * By default kwbimage.cfg from board specific folder is used
38 * If for some board, different configuration file need to be used,
39 * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
41 #ifndef CONFIG_SYS_KWD_CONFIG
42 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
43 #endif /* CONFIG_SYS_KWD_CONFIG */
45 /* Kirkwood has 2k of Security SRAM, use it for SP */
46 #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
48 #define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE
49 #define MV_UART_CONSOLE_BASE KW_UART0_BASE
50 #define MV_SATA_BASE KW_SATA_BASE
51 #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
52 #define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
57 #ifdef CONFIG_CMD_NAND
58 #define CONFIG_NAND_KIRKWOOD
59 #define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
60 #define NAND_ALLOW_ERASE_ALL 1
64 * SPI Flash configuration
67 #ifndef CONFIG_ENV_SPI_BUS
68 # define CONFIG_ENV_SPI_BUS 0
70 #ifndef CONFIG_ENV_SPI_CS
71 # define CONFIG_ENV_SPI_CS 0
73 #ifndef CONFIG_ENV_SPI_MAX_HZ
74 # define CONFIG_ENV_SPI_MAX_HZ 50000000
79 * Ethernet Driver configuration
82 #define CONFIG_NETCONSOLE /* include NetConsole support */
83 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
84 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
85 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
86 #endif /* CONFIG_CMD_NET */
92 #define CONFIG_EHCI_IS_TDI
93 #endif /* CONFIG_CMD_USB */
96 * IDE Support on SATA ports
100 #define CONFIG_IDE_PREINIT
101 #define CONFIG_MVSATA_IDE_USE_PORT1
102 /* Needs byte-swapping for ATA data register */
103 #define CONFIG_IDE_SWAP_IO
104 /* Data, registers and alternate blocks are at the same offset */
105 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
106 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
107 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
108 /* Each 8-bit ATA register is aligned to a 4-bytes address */
109 #define CONFIG_SYS_ATA_STRIDE 4
110 /* Controller supports 48-bits LBA addressing */
112 /* CONFIG_IDE requires some #defines for ATA registers */
113 #define CONFIG_SYS_IDE_MAXBUS 2
114 #define CONFIG_SYS_IDE_MAXDEVICE 2
115 /* ATA registers base is at SATA controller base */
116 #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
117 #endif /* CONFIG_IDE */
122 #if defined(CONFIG_CMD_I2C) && !defined(CONFIG_DM_I2C)
123 #ifndef CONFIG_SYS_I2C_SOFT
124 #define CONFIG_SYS_I2C
125 #define CONFIG_SYS_I2C_MVTWSI
127 #define CONFIG_SYS_I2C_SLAVE 0x0
128 #define CONFIG_SYS_I2C_SPEED 100000
131 /* Use common timer */
132 #define CONFIG_SYS_TIMER_COUNTS_DOWN
133 #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
134 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK
136 #endif /* _KW_CONFIG_H */