1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 #include <asm/cache.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
14 #include <mvebu_mmc.h>
16 void reset_cpu(unsigned long ignored)
18 struct kwcpu_registers *cpureg =
19 (struct kwcpu_registers *)KW_CPU_REG_BASE;
21 writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
22 &cpureg->rstoutn_mask);
23 writel(readl(&cpureg->sys_soft_rst) | 1,
24 &cpureg->sys_soft_rst);
30 * Used with the Base register to set the address window size and location.
31 * Must be programmed from LSB to MSB as sequence of ones followed by
32 * sequence of zeros. The number of ones specifies the size of the window in
33 * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
34 * NOTE: A value of 0x0 specifies 64-KByte size.
36 unsigned int kw_winctrl_calcsize(unsigned int sizeval)
40 u32 val = sizeval >> 1;
42 for (i = 0; val >= 0x10000; i++) {
46 return (0x0000ffff & j);
49 static struct mbus_win windows[] = {
50 /* Window 0: PCIE MEM address space */
51 { KW_DEFADR_PCI_MEM, 1024 * 1024 * 256,
52 KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM },
54 /* Window 1: PCIE IO address space */
55 { KW_DEFADR_PCI_IO, 1024 * 64,
56 KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO },
58 /* Window 2: NAND Flash address space */
59 { KW_DEFADR_NANDF, 1024 * 1024 * 128,
60 KWCPU_TARGET_MEMORY, KWCPU_ATTR_NANDFLASH },
62 /* Window 3: SPI Flash address space */
63 { KW_DEFADR_SPIF, 1024 * 1024 * 128,
64 KWCPU_TARGET_MEMORY, KWCPU_ATTR_SPIFLASH },
66 /* Window 4: BOOT Memory address space */
67 { KW_DEFADR_BOOTROM, 1024 * 1024 * 128,
68 KWCPU_TARGET_MEMORY, KWCPU_ATTR_BOOTROM },
70 /* Window 5: Security SRAM address space */
71 { KW_DEFADR_SASRAM, 1024 * 64,
72 KWCPU_TARGET_SASRAM, KWCPU_ATTR_SASRAM },
76 * SYSRSTn Duration Counter Support
78 * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
79 * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
80 * The SYSRSTn duration counter is useful for implementing a manufacturer
81 * or factory reset. Upon a long reset assertion that is greater than a
82 * pre-configured environment variable value for sysrstdelay,
83 * The counter value is stored in the SYSRSTn Length Counter Register
84 * The counter is based on the 25-MHz reference clock (40ns)
85 * It is a 29-bit counter, yielding a maximum counting duration of
86 * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
87 * it remains at this value until counter reset is triggered by setting
88 * bit 31 of KW_REG_SYSRST_CNT
90 static void kw_sysrst_action(void)
93 char *s = env_get("sysrstcmd");
96 debug("Error.. %s failed, check sysrstcmd\n",
101 debug("Starting %s process...\n", __FUNCTION__);
102 ret = run_command(s, 0);
104 debug("Error.. %s failed\n", __FUNCTION__);
106 debug("%s process finished\n", __FUNCTION__);
109 static void kw_sysrst_check(void)
111 u32 sysrst_cnt, sysrst_dly;
115 * no action if sysrstdelay environment variable is not defined
117 s = env_get("sysrstdelay");
121 /* read sysrstdelay value */
122 sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
124 /* read SysRst Length counter register (bits 28:0) */
125 sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
126 debug("H/w Rst hold time: %d.%d secs\n",
127 sysrst_cnt / SYSRST_CNT_1SEC_VAL,
128 sysrst_cnt % SYSRST_CNT_1SEC_VAL);
130 /* clear the counter for next valid read*/
131 writel(1 << 31, KW_REG_SYSRST_CNT);
135 * if H/w Reset key is pressed and hold for time
136 * more than sysrst_dly in seconds
138 if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
142 #if defined(CONFIG_DISPLAY_CPUINFO)
143 int print_cpuinfo(void)
146 u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
147 u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
149 if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
150 printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
158 else if (devid == 0x6282)
174 printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
177 #endif /* CONFIG_DISPLAY_CPUINFO */
179 #ifdef CONFIG_ARCH_CPU_INIT
180 int arch_cpu_init(void)
183 struct kwcpu_registers *cpureg =
184 (struct kwcpu_registers *)KW_CPU_REG_BASE;
186 /* Linux expects the internal registers to be at 0xf1000000 */
187 writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
189 /* Enable and invalidate L2 cache in write through mode */
190 writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
191 invalidate_l2_cache();
193 #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
195 * Configures the I/O voltage of the pads connected to Egigabit
196 * Ethernet interface to 1.8V
197 * By default it is set to 3.3V
199 reg = readl(KW_REG_MPP_OUT_DRV_REG);
201 writel(reg, KW_REG_MPP_OUT_DRV_REG);
203 #ifdef CONFIG_KIRKWOOD_EGIGA_INIT
205 * Set egiga port0/1 in normal functional mode
206 * This is required becasue on kirkwood by default ports are in reset mode
207 * OS egiga driver may not have provision to set them in normal mode
208 * and if u-boot is build without network support, network may fail at OS level
210 reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
211 reg &= ~(1 << 4); /* Clear PortReset Bit */
212 writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
213 reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
214 reg &= ~(1 << 4); /* Clear PortReset Bit */
215 writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
217 #ifdef CONFIG_KIRKWOOD_PCIE_INIT
219 * Enable PCI Express Port0
221 reg = readl(&cpureg->ctrl_stat);
222 reg |= (1 << 0); /* Set PEX0En Bit */
223 writel(reg, &cpureg->ctrl_stat);
227 #endif /* CONFIG_ARCH_CPU_INIT */
230 * SOC specific misc init
232 #if defined(CONFIG_ARCH_MISC_INIT)
233 int arch_misc_init(void)
237 /*CPU streaming & write allocate */
238 temp = readfr_extra_feature_reg();
239 temp &= ~(1 << 28); /* disable wr alloc */
240 writefr_extra_feature_reg(temp);
242 temp = readfr_extra_feature_reg();
243 temp &= ~(1 << 29); /* streaming disabled */
244 writefr_extra_feature_reg(temp);
246 /* L2Cache settings */
247 temp = readfr_extra_feature_reg();
248 /* Disable L2C pre fetch - Set bit 24 */
250 /* enable L2C - Set bit 22 */
252 writefr_extra_feature_reg(temp);
254 /* Change reset vector to address 0x0 */
256 set_cr(temp & ~CR_V);
258 /* Configure mbus windows */
259 mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
261 /* checks and execute resset to factory event */
266 #endif /* CONFIG_ARCH_MISC_INIT */
269 int cpu_eth_init(bd_t *bis)
271 mvgbe_initialize(bis);
276 #ifdef CONFIG_MVEBU_MMC
277 int board_mmc_init(bd_t *bis)
282 #endif /* CONFIG_MVEBU_MMC */