arch/arm/mach-keystone/clock-k2hk.c

   1 /*
   2  * Keystone2: get clk rate for K2HK
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/clock_defs.h>
  13
  14 /**
  15  * pll_freq_get - get pll frequency
  16  * Fout = Fref * NF(mult) / NR(prediv) / OD
  17  * @pll:        pll identifier
  18  */
  19 static unsigned long pll_freq_get(int pll)
  20 {
  21         unsigned long mult = 1, prediv = 1, output_div = 2;
  22         unsigned long ret;
  23         u32 tmp, reg;
  24
  25         if (pll == CORE_PLL) {
  26                 ret = external_clk[sys_clk];
  27                 if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
  28                         /* PLL mode */
  29                         tmp = __raw_readl(KS2_MAINPLLCTL0);
  30                         prediv = (tmp & PLL_DIV_MASK) + 1;
  31                         mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
  32                                 (pllctl_reg_read(pll, mult) &
  33                                  PLLM_MULT_LO_MASK)) + 1;
  34                         output_div = ((pllctl_reg_read(pll, secctl) >>
  35                                        PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
  36
  37                         ret = ret / prediv / output_div * mult;
  38                 }
  39         } else {
  40                 switch (pll) {
  41                 case PASS_PLL:
  42                         ret = external_clk[pa_clk];
  43                         reg = KS2_PASSPLLCTL0;
  44                         break;
  45                 case TETRIS_PLL:
  46                         ret = external_clk[tetris_clk];
  47                         reg = KS2_ARMPLLCTL0;
  48                         break;
  49                 case DDR3A_PLL:
  50                         ret = external_clk[ddr3a_clk];
  51                         reg = KS2_DDR3APLLCTL0;
  52                         break;
  53                 case DDR3B_PLL:
  54                         ret = external_clk[ddr3b_clk];
  55                         reg = KS2_DDR3BPLLCTL0;
  56                         break;
  57                 default:
  58                         return 0;
  59                 }
  60
  61                 tmp = __raw_readl(reg);
  62
  63                 if (!(tmp & PLLCTL_BYPASS)) {
  64                         /* Bypass disabled */
  65                         prediv = (tmp & PLL_DIV_MASK) + 1;
  66                         mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
  67                         output_div = ((tmp >> PLL_CLKOD_SHIFT) &
  68                                       PLL_CLKOD_MASK) + 1;
  69                         ret = ((ret / prediv) * mult) / output_div;
  70                 }
  71         }
  72
  73         return ret;
  74 }
  75
  76 unsigned long clk_get_rate(unsigned int clk)
  77 {
  78         switch (clk) {
  79         case core_pll_clk:      return pll_freq_get(CORE_PLL);
  80         case pass_pll_clk:      return pll_freq_get(PASS_PLL);
  81         case tetris_pll_clk:    return pll_freq_get(TETRIS_PLL);
  82         case ddr3a_pll_clk:     return pll_freq_get(DDR3A_PLL);
  83         case ddr3b_pll_clk:     return pll_freq_get(DDR3B_PLL);
  84         case sys_clk0_1_clk:
  85         case sys_clk0_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(1);
  86         case sys_clk1_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(2);
  87         case sys_clk2_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(3);
  88         case sys_clk3_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(4);
  89         case sys_clk0_2_clk:    return clk_get_rate(sys_clk0_clk) / 2;
  90         case sys_clk0_3_clk:    return clk_get_rate(sys_clk0_clk) / 3;
  91         case sys_clk0_4_clk:    return clk_get_rate(sys_clk0_clk) / 4;
  92         case sys_clk0_6_clk:    return clk_get_rate(sys_clk0_clk) / 6;
  93         case sys_clk0_8_clk:    return clk_get_rate(sys_clk0_clk) / 8;
  94         case sys_clk0_12_clk:   return clk_get_rate(sys_clk0_clk) / 12;
  95         case sys_clk0_24_clk:   return clk_get_rate(sys_clk0_clk) / 24;
  96         case sys_clk1_3_clk:    return clk_get_rate(sys_clk1_clk) / 3;
  97         case sys_clk1_4_clk:    return clk_get_rate(sys_clk1_clk) / 4;
  98         case sys_clk1_6_clk:    return clk_get_rate(sys_clk1_clk) / 6;
  99         case sys_clk1_12_clk:   return clk_get_rate(sys_clk1_clk) / 12;
 100         default:
 101                 break;
 102         }
 103
 104         return 0;
 105 }