1 // SPDX-License-Identifier: GPL-2.0+
3 * J721E: SoC specific initialization
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
12 #include <asm/armv7_mpu.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/sysfw-loader.h>
16 #include <asm/arch/sys_proto.h>
17 #include <linux/soc/ti/ti_sci_protocol.h>
19 #include <dm/uclass-internal.h>
20 #include <dm/pinctrl.h>
22 #ifdef CONFIG_SPL_BUILD
23 #ifdef CONFIG_K3_LOAD_SYSFW
24 #ifdef CONFIG_TI_SECURE_DEVICE
25 struct fwl_data cbass_hc_cfg0_fwls[] = {
26 { "PCIE0_CFG", 2560, 8 },
27 { "PCIE1_CFG", 2561, 8 },
28 { "USB3SS0_CORE", 2568, 4 },
29 { "USB3SS1_CORE", 2570, 4 },
30 { "EMMC8SS0_CFG", 2576, 4 },
31 { "UFS_HCI0_CFG", 2580, 4 },
32 { "SERDES0", 2584, 1 },
33 { "SERDES1", 2585, 1 },
34 }, cbass_hc0_fwls[] = {
35 { "PCIE0_HP", 2528, 24 },
36 { "PCIE0_LP", 2529, 24 },
37 { "PCIE1_HP", 2530, 24 },
38 { "PCIE1_LP", 2531, 24 },
39 }, cbass_rc_cfg0_fwls[] = {
40 { "EMMCSD4SS0_CFG", 2380, 4 },
41 }, cbass_rc0_fwls[] = {
43 }, infra_cbass0_fwls[] = {
44 { "PLL_MMR0", 8, 26 },
45 { "CTRL_MMR0", 9, 16 },
46 }, mcu_cbass0_fwls[] = {
47 { "MCU_R5FSS0_CORE0", 1024, 4 },
48 { "MCU_R5FSS0_CORE0_CFG", 1025, 2 },
49 { "MCU_R5FSS0_CORE1", 1028, 4 },
50 { "MCU_FSS0_CFG", 1032, 12 },
51 { "MCU_FSS0_S1", 1033, 8 },
52 { "MCU_FSS0_S0", 1036, 8 },
53 { "MCU_PSROM49152X32", 1048, 1 },
54 { "MCU_MSRAM128KX64", 1050, 8 },
55 { "MCU_CTRL_MMR0", 1200, 8 },
56 { "MCU_PLL_MMR0", 1201, 3 },
57 { "MCU_CPSW0", 1220, 2 },
58 }, wkup_cbass0_fwls[] = {
59 { "WKUP_CTRL_MMR0", 131, 16 },
64 static void mmr_unlock(u32 base, u32 partition)
66 /* Translate the base address */
67 phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
69 /* Unlock the requested partition if locked using two-step sequence */
70 writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
71 writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
74 static void ctrl_mmr_unlock(void)
76 /* Unlock all WKUP_CTRL_MMR0 module registers */
77 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
78 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
79 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
80 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
81 mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
82 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
83 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
85 /* Unlock all MCU_CTRL_MMR0 module registers */
86 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
87 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
88 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
89 mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
90 mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
92 /* Unlock all CTRL_MMR0 module registers */
93 mmr_unlock(CTRL_MMR0_BASE, 0);
94 mmr_unlock(CTRL_MMR0_BASE, 1);
95 mmr_unlock(CTRL_MMR0_BASE, 2);
96 mmr_unlock(CTRL_MMR0_BASE, 3);
97 mmr_unlock(CTRL_MMR0_BASE, 4);
98 mmr_unlock(CTRL_MMR0_BASE, 5);
99 mmr_unlock(CTRL_MMR0_BASE, 6);
100 mmr_unlock(CTRL_MMR0_BASE, 7);
104 * This uninitialized global variable would normal end up in the .bss section,
105 * but the .bss is cleared between writing and reading this variable, so move
106 * it to the .data section.
108 u32 bootindex __attribute__((section(".data")));
110 static void store_boot_index_from_rom(void)
112 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
115 void board_init_f(ulong dummy)
117 #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
122 * Cannot delay this further as there is a chance that
123 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
125 store_boot_index_from_rom();
127 /* Make all control module registers accessible */
130 #ifdef CONFIG_CPU_V7R
131 disable_linefill_optimization();
132 setup_k3_mpu_regions();
138 #ifdef CONFIG_K3_LOAD_SYSFW
140 * Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue
141 * regardless of the result of pinctrl. Do this without probing the
142 * device, but instead by searching the device that would request the
143 * given sequence number if probed. The UART will be used by the system
144 * firmware (SYSFW) image for various purposes and SYSFW depends on us
145 * to initialize its pin settings.
147 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
149 pinctrl_select_state(dev, "default");
152 * Load, start up, and configure system controller firmware. Provide
153 * the U-Boot console init function to the SYSFW post-PM configuration
154 * callback hook, effectively switching on (or over) the console
157 k3_sysfw_loader(preloader_console_init);
159 /* Disable ROM configured firewalls right after loading sysfw */
160 #ifdef CONFIG_TI_SECURE_DEVICE
161 remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
162 remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls));
163 remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
164 remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls));
165 remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
166 remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
167 remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
170 /* Prepare console output */
171 preloader_console_init();
174 /* Perform EEPROM-based board detection */
177 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
178 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
181 printf("AVS init failed: %d\n", ret);
184 #if defined(CONFIG_K3_J721E_DDRSS)
185 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
187 panic("DRAM init failed: %d\n", ret);
191 u32 spl_boot_mode(const u32 boot_device)
193 switch (boot_device) {
194 case BOOT_DEVICE_MMC1:
195 return MMCSD_MODE_EMMCBOOT;
196 case BOOT_DEVICE_MMC2:
197 return MMCSD_MODE_FS;
199 return MMCSD_MODE_RAW;
203 static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
206 u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
207 WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
209 bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
212 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
213 bootmode = BOOT_DEVICE_SPI;
215 if (bootmode == BOOT_DEVICE_MMC2) {
216 u32 port = (main_devstat &
217 MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
218 MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
220 bootmode = BOOT_DEVICE_MMC1;
226 u32 spl_boot_device(void)
228 u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
231 if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
232 printf("ERROR: MCU only boot is not yet supported\n");
233 return BOOT_DEVICE_RAM;
236 /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
237 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
239 /* ToDo: Add support for backup boot media */
240 return __get_primary_bootmedia(main_devstat, wkup_devstat);
244 #ifdef CONFIG_SYS_K3_SPL_ATF
246 #define J721E_DEV_MCU_RTI0 262
247 #define J721E_DEV_MCU_RTI1 263
248 #define J721E_DEV_MCU_ARMSS0_CPU0 250
249 #define J721E_DEV_MCU_ARMSS0_CPU1 251
251 void release_resources_for_core_shutdown(void)
253 struct ti_sci_handle *ti_sci;
254 struct ti_sci_dev_ops *dev_ops;
255 struct ti_sci_proc_ops *proc_ops;
259 const u32 put_device_ids[] = {
264 ti_sci = get_ti_sci_handle();
265 dev_ops = &ti_sci->ops.dev_ops;
266 proc_ops = &ti_sci->ops.proc_ops;
268 /* Iterate through list of devices to put (shutdown) */
269 for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
270 u32 id = put_device_ids[i];
272 ret = dev_ops->put_device(ti_sci, id);
274 panic("Failed to put device %u (%d)\n", id, ret);
277 const u32 put_core_ids[] = {
278 J721E_DEV_MCU_ARMSS0_CPU1,
279 J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
282 /* Iterate through list of cores to put (shutdown) */
283 for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
284 u32 id = put_core_ids[i];
287 * Queue up the core shutdown request. Note that this call
288 * needs to be followed up by an actual invocation of an WFE
289 * or WFI CPU instruction.
291 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
293 panic("Failed sending core %u shutdown message (%d)\n",