1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * K3: AM6 SoC definitions, structures etc.
5 * (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
7 #ifndef __ASM_ARCH_AM6_HARDWARE_H
8 #define __ASM_ARCH_AM6_HARDWARE_H
12 #define CTRL_MMR0_BASE 0x00100000
13 #define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
15 #define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK GENMASK(3, 0)
16 #define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT 0
17 #define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(6, 4)
18 #define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 4
19 #define CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK GENMASK(12, 12)
20 #define CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT 12
21 #define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK GENMASK(14, 14)
22 #define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT 14
23 #define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK GENMASK(17, 17)
24 #define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 12
26 #define WKUP_CTRL_MMR0_BASE 0x43000000
27 #define MCU_CTRL_MMR0_BASE 0x40f00000
30 * The CTRL_MMR0 memory space is divided into several equally-spaced
31 * partitions, so defining the partition size allows us to determine
32 * register addresses common to those partitions.
34 #define CTRL_MMR0_PARTITION_SIZE 0x4000
37 * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
38 * shared register definitions.
40 #define CTRLMMR_LOCK_KICK0 0x01008
41 #define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
42 #define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
43 #define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
44 #define CTRLMMR_LOCK_KICK1 0x0100c
45 #define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
47 /* MCU SCRATCHPAD usage */
48 #define K3_BOOT_PARAM_TABLE_INDEX_VAL CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
50 #endif /* __ASM_ARCH_AM6_HARDWARE_H */