arch/arm/mach-k3/arm64-mmu.c

   1 // SPDX-License-Identifier:     GPL-2.0+
   2 /*
   3  * K3: ARM64 MMU setup
   4  *
   5  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  * (This file is derived from arch/arm/mach-zynqmp/cpu.c)
   8  *
   9  */
  10
  11 #include <common.h>
  12 #include <asm/system.h>
  13 #include <asm/armv8/mmu.h>
  14
  15 #ifdef CONFIG_SOC_K3_AM6
  16 /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
  17 #define NR_MMU_REGIONS  (CONFIG_NR_DRAM_BANKS + 3)
  18
  19 /* ToDo: Add 64bit IO */
  20 struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
  21         {
  22                 .virt = 0x0UL,
  23                 .phys = 0x0UL,
  24                 .size = 0x80000000UL,
  25                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  26                          PTE_BLOCK_NON_SHARE |
  27                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  28         }, {
  29                 .virt = 0x80000000UL,
  30                 .phys = 0x80000000UL,
  31                 .size = 0x80000000UL,
  32                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  33                          PTE_BLOCK_INNER_SHARE
  34         }, {
  35                 .virt = 0x880000000UL,
  36                 .phys = 0x880000000UL,
  37                 .size = 0x80000000UL,
  38                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  39                          PTE_BLOCK_INNER_SHARE
  40         }, {
  41                 /* List terminator */
  42                 0,
  43         }
  44 };
  45
  46 struct mm_region *mem_map = am654_mem_map;
  47 #endif /* CONFIG_SOC_K3_AM6 */
  48
  49 #ifdef CONFIG_SOC_K3_J721E
  50 /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
  51 #define NR_MMU_REGIONS  (CONFIG_NR_DRAM_BANKS + 5)
  52
  53 /* ToDo: Add 64bit IO */
  54 struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
  55         {
  56                 .virt = 0x0UL,
  57                 .phys = 0x0UL,
  58                 .size = 0x80000000UL,
  59                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  60                          PTE_BLOCK_NON_SHARE |
  61                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  62         }, {
  63                 .virt = 0x80000000UL,
  64                 .phys = 0x80000000UL,
  65                 .size = 0x20000000UL,
  66                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  67                          PTE_BLOCK_INNER_SHARE
  68         }, {
  69                 .virt = 0xa0000000UL,
  70                 .phys = 0xa0000000UL,
  71                 .size = 0x0bc00000UL,
  72                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
  73                          PTE_BLOCK_NON_SHARE
  74         }, {
  75                 .virt = 0xabc00000UL,
  76                 .phys = 0xabc00000UL,
  77                 .size = 0x54400000UL,
  78                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  79                          PTE_BLOCK_INNER_SHARE
  80         }, {
  81                 .virt = 0x880000000UL,
  82                 .phys = 0x880000000UL,
  83                 .size = 0x80000000UL,
  84                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  85                          PTE_BLOCK_INNER_SHARE
  86         }, {
  87                 .virt = 0x500000000UL,
  88                 .phys = 0x500000000UL,
  89                 .size = 0x400000000UL,
  90                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  91                          PTE_BLOCK_NON_SHARE |
  92                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  93         }, {
  94                 /* List terminator */
  95                 0,
  96         }
  97 };
  98
  99 struct mm_region *mem_map = j721e_mem_map;
 100 #endif /* CONFIG_SOC_K3_J721E */