arch/arm/mach-k3/arm64-mmu.c

   1 // SPDX-License-Identifier:     GPL-2.0+
   2 /*
   3  * K3: ARM64 MMU setup
   4  *
   5  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  * (This file is derived from arch/arm/mach-zynqmp/cpu.c)
   8  *
   9  */
  10
  11 #include <common.h>
  12 #include <asm/system.h>
  13 #include <asm/armv8/mmu.h>
  14
  15 #ifdef CONFIG_SOC_K3_AM6
  16 /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
  17 #define NR_MMU_REGIONS  (CONFIG_NR_DRAM_BANKS + 5)
  18
  19 /* ToDo: Add 64bit IO */
  20 struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
  21         {
  22                 .virt = 0x0UL,
  23                 .phys = 0x0UL,
  24                 .size = 0x80000000UL,
  25                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  26                          PTE_BLOCK_NON_SHARE |
  27                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  28         }, {
  29                 .virt = 0x80000000UL,
  30                 .phys = 0x80000000UL,
  31                 .size = 0x20000000UL,
  32                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  33                          PTE_BLOCK_INNER_SHARE
  34         }, {
  35                 .virt = 0xa0000000UL,
  36                 .phys = 0xa0000000UL,
  37                 .size = 0x02100000UL,
  38                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
  39                          PTE_BLOCK_INNER_SHARE
  40         }, {
  41                 .virt = 0xa2100000UL,
  42                 .phys = 0xa2100000UL,
  43                 .size = 0x5df00000UL,
  44                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  45                          PTE_BLOCK_INNER_SHARE
  46         }, {
  47                 .virt = 0x880000000UL,
  48                 .phys = 0x880000000UL,
  49                 .size = 0x80000000UL,
  50                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  51                          PTE_BLOCK_INNER_SHARE
  52         }, {
  53                 .virt = 0x500000000UL,
  54                 .phys = 0x500000000UL,
  55                 .size = 0x400000000UL,
  56                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  57                          PTE_BLOCK_NON_SHARE |
  58                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  59         }, {
  60                 /* List terminator */
  61                 0,
  62         }
  63 };
  64
  65 struct mm_region *mem_map = am654_mem_map;
  66 #endif /* CONFIG_SOC_K3_AM6 */
  67
  68 #ifdef CONFIG_SOC_K3_J721E
  69 /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
  70 #define NR_MMU_REGIONS  (CONFIG_NR_DRAM_BANKS + 6)
  71
  72 /* ToDo: Add 64bit IO */
  73 struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
  74         {
  75                 .virt = 0x0UL,
  76                 .phys = 0x0UL,
  77                 .size = 0x80000000UL,
  78                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  79                          PTE_BLOCK_NON_SHARE |
  80                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  81         }, {
  82                 .virt = 0x80000000UL,
  83                 .phys = 0x80000000UL,
  84                 .size = 0x20000000UL,
  85                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  86                          PTE_BLOCK_INNER_SHARE
  87         }, {
  88                 .virt = 0xa0000000UL,
  89                 .phys = 0xa0000000UL,
  90                 .size = 0x1bc00000UL,
  91                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
  92                          PTE_BLOCK_NON_SHARE
  93         }, {
  94                 .virt = 0xbbc00000UL,
  95                 .phys = 0xbbc00000UL,
  96                 .size = 0x44400000UL,
  97                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  98                          PTE_BLOCK_INNER_SHARE
  99         }, {
 100                 .virt = 0x880000000UL,
 101                 .phys = 0x880000000UL,
 102                 .size = 0x80000000UL,
 103                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 104                          PTE_BLOCK_INNER_SHARE
 105         }, {
 106                 .virt = 0x500000000UL,
 107                 .phys = 0x500000000UL,
 108                 .size = 0x400000000UL,
 109                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 110                          PTE_BLOCK_NON_SHARE |
 111                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 112         }, {
 113                 .virt = 0x4d80000000UL,
 114                 .phys = 0x4d80000000UL,
 115                 .size = 0x0002000000UL,
 116                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
 117                          PTE_BLOCK_INNER_SHARE
 118         }, {
 119                 /* List terminator */
 120                 0,
 121         }
 122 };
 123
 124 struct mm_region *mem_map = j721e_mem_map;
 125 #endif /* CONFIG_SOC_K3_J721E */