1 // SPDX-License-Identifier: GPL-2.0+
3 * K3: Architecture initialization
5 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
12 #include <asm/arch/hardware.h>
16 #ifdef CONFIG_SPL_BUILD
17 static void mmr_unlock(u32 base, u32 partition)
19 /* Translate the base address */
20 phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
22 /* Unlock the requested partition if locked using two-step sequence */
23 writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
24 writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
27 static void ctrl_mmr_unlock(void)
29 /* Unlock all WKUP_CTRL_MMR0 module registers */
30 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
31 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
32 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
33 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
34 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
35 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
37 /* Unlock all MCU_CTRL_MMR0 module registers */
38 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
39 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
40 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
41 mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
43 /* Unlock all CTRL_MMR0 module registers */
44 mmr_unlock(CTRL_MMR0_BASE, 0);
45 mmr_unlock(CTRL_MMR0_BASE, 1);
46 mmr_unlock(CTRL_MMR0_BASE, 2);
47 mmr_unlock(CTRL_MMR0_BASE, 3);
48 mmr_unlock(CTRL_MMR0_BASE, 6);
49 mmr_unlock(CTRL_MMR0_BASE, 7);
52 static void store_boot_index_from_rom(void)
54 u32 *boot_index = (u32 *)K3_BOOT_PARAM_TABLE_INDEX_VAL;
56 *boot_index = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
59 void board_init_f(ulong dummy)
61 #if defined(CONFIG_K3_AM654_DDRSS)
66 * Cannot delay this further as there is a chance that
67 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
69 store_boot_index_from_rom();
71 /* Make all control module registers accessible */
75 setup_k3_mpu_regions();
78 /* Init DM early in-order to invoke system controller */
81 /* Prepare console output */
82 preloader_console_init();
84 #ifdef CONFIG_K3_AM654_DDRSS
85 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
87 printf("DRAM init failed: %d\n", ret);
93 u32 spl_boot_mode(const u32 boot_device)
95 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
96 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
97 u32 bootindex = readl(K3_BOOT_PARAM_TABLE_INDEX_VAL);
99 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
100 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
102 /* eMMC boot0 mode is only supported for primary boot */
103 if (bootindex == K3_PRIMARY_BOOTMODE &&
104 bootmode == BOOT_DEVICE_MMC1)
105 return MMCSD_MODE_EMMCBOOT;
108 /* Everything else use filesystem if available */
109 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
110 return MMCSD_MODE_FS;
112 return MMCSD_MODE_RAW;
116 static u32 __get_backup_bootmedia(u32 devstat)
118 u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
119 CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
122 case BACKUP_BOOT_DEVICE_USB:
123 return BOOT_DEVICE_USB;
124 case BACKUP_BOOT_DEVICE_UART:
125 return BOOT_DEVICE_UART;
126 case BACKUP_BOOT_DEVICE_ETHERNET:
127 return BOOT_DEVICE_ETHERNET;
128 case BACKUP_BOOT_DEVICE_MMC2:
130 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
131 CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
133 return BOOT_DEVICE_MMC1;
134 return BOOT_DEVICE_MMC2;
136 case BACKUP_BOOT_DEVICE_SPI:
137 return BOOT_DEVICE_SPI;
138 case BACKUP_BOOT_DEVICE_HYPERFLASH:
139 return BOOT_DEVICE_HYPERFLASH;
140 case BACKUP_BOOT_DEVICE_I2C:
141 return BOOT_DEVICE_I2C;
144 return BOOT_DEVICE_RAM;
147 static u32 __get_primary_bootmedia(u32 devstat)
149 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
150 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
152 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
153 bootmode = BOOT_DEVICE_SPI;
155 if (bootmode == BOOT_DEVICE_MMC2) {
156 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
157 CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
159 bootmode = BOOT_DEVICE_MMC1;
160 } else if (bootmode == BOOT_DEVICE_MMC1) {
161 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
162 CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
164 bootmode = BOOT_DEVICE_MMC2;
170 u32 spl_boot_device(void)
172 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
173 u32 bootindex = readl(K3_BOOT_PARAM_TABLE_INDEX_VAL);
175 if (bootindex == K3_PRIMARY_BOOTMODE)
176 return __get_primary_bootmedia(devstat);
178 return __get_backup_bootmedia(devstat);
182 #ifndef CONFIG_SYSRESET
183 void reset_cpu(ulong ignored)