1 // SPDX-License-Identifier: GPL-2.0+
3 * K3: Architecture initialization
5 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/sysfw-loader.h>
14 #include <asm/arch/sys_proto.h>
17 #include <dm/uclass-internal.h>
18 #include <dm/pinctrl.h>
20 #ifdef CONFIG_SPL_BUILD
21 static void mmr_unlock(u32 base, u32 partition)
23 /* Translate the base address */
24 phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
26 /* Unlock the requested partition if locked using two-step sequence */
27 writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
28 writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
31 static void ctrl_mmr_unlock(void)
33 /* Unlock all WKUP_CTRL_MMR0 module registers */
34 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
35 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
36 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
37 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
38 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
39 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
41 /* Unlock all MCU_CTRL_MMR0 module registers */
42 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
43 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
44 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
45 mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
47 /* Unlock all CTRL_MMR0 module registers */
48 mmr_unlock(CTRL_MMR0_BASE, 0);
49 mmr_unlock(CTRL_MMR0_BASE, 1);
50 mmr_unlock(CTRL_MMR0_BASE, 2);
51 mmr_unlock(CTRL_MMR0_BASE, 3);
52 mmr_unlock(CTRL_MMR0_BASE, 6);
53 mmr_unlock(CTRL_MMR0_BASE, 7);
57 * This uninitialized global variable would normal end up in the .bss section,
58 * but the .bss is cleared between writing and reading this variable, so move
59 * it to the .data section.
61 u32 bootindex __attribute__((section(".data")));
63 static void store_boot_index_from_rom(void)
65 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
68 void board_init_f(ulong dummy)
70 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
75 * Cannot delay this further as there is a chance that
76 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
78 store_boot_index_from_rom();
80 /* Make all control module registers accessible */
84 setup_k3_mpu_regions();
87 /* Init DM early in-order to invoke system controller */
90 #ifdef CONFIG_K3_LOAD_SYSFW
92 * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
93 * regardless of the result of pinctrl. Do this without probing the
94 * device, but instead by searching the device that would request the
95 * given sequence number if probed. The UART will be used by the system
96 * firmware (SYSFW) image for various purposes and SYSFW depends on us
97 * to initialize its pin settings.
99 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
101 pinctrl_select_state(dev, "default");
104 * Load, start up, and configure system controller firmware. Provide
105 * the U-Boot console init function to the SYSFW post-PM configuration
106 * callback hook, effectively switching on (or over) the console
109 k3_sysfw_loader(preloader_console_init);
111 /* Prepare console output */
112 preloader_console_init();
115 /* Perform EEPROM-based board detection */
118 #ifdef CONFIG_K3_AM654_DDRSS
119 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
121 panic("DRAM init failed: %d\n", ret);
125 u32 spl_boot_mode(const u32 boot_device)
127 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
128 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
130 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
131 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
133 /* eMMC boot0 mode is only supported for primary boot */
134 if (bootindex == K3_PRIMARY_BOOTMODE &&
135 bootmode == BOOT_DEVICE_MMC1)
136 return MMCSD_MODE_EMMCBOOT;
139 /* Everything else use filesystem if available */
140 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
141 return MMCSD_MODE_FS;
143 return MMCSD_MODE_RAW;
147 static u32 __get_backup_bootmedia(u32 devstat)
149 u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
150 CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
153 case BACKUP_BOOT_DEVICE_USB:
154 return BOOT_DEVICE_USB;
155 case BACKUP_BOOT_DEVICE_UART:
156 return BOOT_DEVICE_UART;
157 case BACKUP_BOOT_DEVICE_ETHERNET:
158 return BOOT_DEVICE_ETHERNET;
159 case BACKUP_BOOT_DEVICE_MMC2:
161 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
162 CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
164 return BOOT_DEVICE_MMC1;
165 return BOOT_DEVICE_MMC2;
167 case BACKUP_BOOT_DEVICE_SPI:
168 return BOOT_DEVICE_SPI;
169 case BACKUP_BOOT_DEVICE_HYPERFLASH:
170 return BOOT_DEVICE_HYPERFLASH;
171 case BACKUP_BOOT_DEVICE_I2C:
172 return BOOT_DEVICE_I2C;
175 return BOOT_DEVICE_RAM;
178 static u32 __get_primary_bootmedia(u32 devstat)
180 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
181 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
183 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
184 bootmode = BOOT_DEVICE_SPI;
186 if (bootmode == BOOT_DEVICE_MMC2) {
187 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
188 CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
190 bootmode = BOOT_DEVICE_MMC1;
191 } else if (bootmode == BOOT_DEVICE_MMC1) {
192 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
193 CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
195 bootmode = BOOT_DEVICE_MMC2;
201 u32 spl_boot_device(void)
203 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
205 if (bootindex == K3_PRIMARY_BOOTMODE)
206 return __get_primary_bootmedia(devstat);
208 return __get_backup_bootmedia(devstat);
212 #ifndef CONFIG_SYSRESET
213 void reset_cpu(ulong ignored)