1 // SPDX-License-Identifier: GPL-2.0+
3 * K3: Architecture initialization
5 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/sysfw-loader.h>
14 #include <asm/arch/sys_proto.h>
17 #include <dm/uclass-internal.h>
18 #include <dm/pinctrl.h>
19 #include <linux/soc/ti/ti_sci_protocol.h>
21 #ifdef CONFIG_SPL_BUILD
22 static void mmr_unlock(u32 base, u32 partition)
24 /* Translate the base address */
25 phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
27 /* Unlock the requested partition if locked using two-step sequence */
28 writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
29 writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
32 static void ctrl_mmr_unlock(void)
34 /* Unlock all WKUP_CTRL_MMR0 module registers */
35 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
36 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
37 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
38 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
39 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
40 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
42 /* Unlock all MCU_CTRL_MMR0 module registers */
43 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
44 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
45 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
46 mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
48 /* Unlock all CTRL_MMR0 module registers */
49 mmr_unlock(CTRL_MMR0_BASE, 0);
50 mmr_unlock(CTRL_MMR0_BASE, 1);
51 mmr_unlock(CTRL_MMR0_BASE, 2);
52 mmr_unlock(CTRL_MMR0_BASE, 3);
53 mmr_unlock(CTRL_MMR0_BASE, 6);
54 mmr_unlock(CTRL_MMR0_BASE, 7);
58 * This uninitialized global variable would normal end up in the .bss section,
59 * but the .bss is cleared between writing and reading this variable, so move
60 * it to the .data section.
62 u32 bootindex __attribute__((section(".data")));
64 static void store_boot_index_from_rom(void)
66 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
69 void board_init_f(ulong dummy)
71 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
76 * Cannot delay this further as there is a chance that
77 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
79 store_boot_index_from_rom();
81 /* Make all control module registers accessible */
85 disable_linefill_optimization();
86 setup_k3_mpu_regions();
89 /* Init DM early in-order to invoke system controller */
92 #ifdef CONFIG_K3_LOAD_SYSFW
94 * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
95 * regardless of the result of pinctrl. Do this without probing the
96 * device, but instead by searching the device that would request the
97 * given sequence number if probed. The UART will be used by the system
98 * firmware (SYSFW) image for various purposes and SYSFW depends on us
99 * to initialize its pin settings.
101 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
103 pinctrl_select_state(dev, "default");
106 * Load, start up, and configure system controller firmware. Provide
107 * the U-Boot console init function to the SYSFW post-PM configuration
108 * callback hook, effectively switching on (or over) the console
111 k3_sysfw_loader(preloader_console_init);
113 /* Prepare console output */
114 preloader_console_init();
117 /* Perform EEPROM-based board detection */
120 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
121 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
124 printf("AVS init failed: %d\n", ret);
127 #ifdef CONFIG_K3_AM654_DDRSS
128 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
130 panic("DRAM init failed: %d\n", ret);
134 u32 spl_boot_mode(const u32 boot_device)
136 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
137 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
139 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
140 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
142 /* eMMC boot0 mode is only supported for primary boot */
143 if (bootindex == K3_PRIMARY_BOOTMODE &&
144 bootmode == BOOT_DEVICE_MMC1)
145 return MMCSD_MODE_EMMCBOOT;
148 /* Everything else use filesystem if available */
149 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
150 return MMCSD_MODE_FS;
152 return MMCSD_MODE_RAW;
156 static u32 __get_backup_bootmedia(u32 devstat)
158 u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
159 CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
162 case BACKUP_BOOT_DEVICE_USB:
163 return BOOT_DEVICE_USB;
164 case BACKUP_BOOT_DEVICE_UART:
165 return BOOT_DEVICE_UART;
166 case BACKUP_BOOT_DEVICE_ETHERNET:
167 return BOOT_DEVICE_ETHERNET;
168 case BACKUP_BOOT_DEVICE_MMC2:
170 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
171 CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
173 return BOOT_DEVICE_MMC1;
174 return BOOT_DEVICE_MMC2;
176 case BACKUP_BOOT_DEVICE_SPI:
177 return BOOT_DEVICE_SPI;
178 case BACKUP_BOOT_DEVICE_HYPERFLASH:
179 return BOOT_DEVICE_HYPERFLASH;
180 case BACKUP_BOOT_DEVICE_I2C:
181 return BOOT_DEVICE_I2C;
184 return BOOT_DEVICE_RAM;
187 static u32 __get_primary_bootmedia(u32 devstat)
189 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
190 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
192 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
193 bootmode = BOOT_DEVICE_SPI;
195 if (bootmode == BOOT_DEVICE_MMC2) {
196 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
197 CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
199 bootmode = BOOT_DEVICE_MMC1;
200 } else if (bootmode == BOOT_DEVICE_MMC1) {
201 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
202 CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
204 bootmode = BOOT_DEVICE_MMC2;
210 u32 spl_boot_device(void)
212 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
214 if (bootindex == K3_PRIMARY_BOOTMODE)
215 return __get_primary_bootmedia(devstat);
217 return __get_backup_bootmedia(devstat);
221 #ifdef CONFIG_SYS_K3_SPL_ATF
223 #define AM6_DEV_MCU_RTI0 134
224 #define AM6_DEV_MCU_RTI1 135
225 #define AM6_DEV_MCU_ARMSS0_CPU0 159
226 #define AM6_DEV_MCU_ARMSS0_CPU1 245
228 void release_resources_for_core_shutdown(void)
230 struct ti_sci_handle *ti_sci = get_ti_sci_handle();
231 struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
232 struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
236 const u32 put_device_ids[] = {
241 /* Iterate through list of devices to put (shutdown) */
242 for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
243 u32 id = put_device_ids[i];
245 ret = dev_ops->put_device(ti_sci, id);
247 panic("Failed to put device %u (%d)\n", id, ret);
250 const u32 put_core_ids[] = {
251 AM6_DEV_MCU_ARMSS0_CPU1,
252 AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
255 /* Iterate through list of cores to put (shutdown) */
256 for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
257 u32 id = put_core_ids[i];
260 * Queue up the core shutdown request. Note that this call
261 * needs to be followed up by an actual invocation of an WFE
262 * or WFI CPU instruction.
264 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
266 panic("Failed sending core %u shutdown message (%d)\n",