4 * Peng Fan <peng.fan@nxp.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/mach-imx/hab.h>
15 #include <asm/mach-imx/boot_mode.h>
16 #include <asm/mach-imx/syscounter.h>
17 #include <asm/armv8/mmu.h>
19 #include <fdt_support.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #if defined(CONFIG_SECURE_BOOT)
26 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
34 #ifdef CONFIG_SPL_BUILD
35 struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
36 unsigned long freq = readl(&sctr->cntfid0);
38 /* Update with accurate clock frequency */
39 asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
41 clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
42 SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
51 void enable_tzc380(void)
53 struct iomuxc_gpr_base_regs *gpr =
54 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
56 /* Enable TZASC and lock setting */
57 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
58 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
61 void set_wdog_reset(struct wdog_regs *wdog)
64 * Output WDOG_B signal to reset external pmic or POR_B decided by
65 * the board design. Without external reset, the peripherals/DDR/
66 * PMIC are not reset, that may cause system working abnormal.
67 * WDZST bit is write-once only bit. Align this bit in kernel,
68 * otherwise kernel code will have no chance to set this bit.
70 setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
73 static struct mm_region imx8m_mem_map[] = {
79 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
86 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
93 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
95 PTE_BLOCK_PXN | PTE_BLOCK_UXN
100 .size = 0xC0000000UL,
101 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
102 PTE_BLOCK_OUTER_SHARE
105 .virt = 0x100000000UL,
106 .phys = 0x100000000UL,
107 .size = 0x040000000UL,
108 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
109 PTE_BLOCK_OUTER_SHARE
111 /* List terminator */
116 struct mm_region *mem_map = imx8m_mem_map;
118 u32 get_cpu_rev(void)
120 struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
121 u32 reg = readl(&ana_pll->digprog);
122 u32 type = (reg >> 16) & 0xff;
127 if (reg == CHIP_REV_1_0) {
129 * For B0 chip, the DIGPROG is not updated, still TO1.0.
130 * we have to check ROM version further
132 rom_version = readl((void __iomem *)ROM_VERSION_A0);
133 if (rom_version != CHIP_REV_1_0) {
134 rom_version = readl((void __iomem *)ROM_VERSION_B0);
135 if (rom_version >= CHIP_REV_2_0)
140 return (type << 12) | reg;
143 static void imx_set_wdog_powerdown(bool enable)
145 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
146 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
147 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
149 /* Write to the PDE (Power Down Enable) bit */
150 writew(enable, &wdog1->wmcr);
151 writew(enable, &wdog2->wmcr);
152 writew(enable, &wdog3->wmcr);
155 int arch_cpu_init(void)
158 * Init timer at very early state, because sscg pll setting
163 if (IS_ENABLED(CONFIG_SPL_BUILD)) {
165 imx_set_wdog_powerdown(false);
171 bool is_usb_boot(void)
173 return get_boot_device() == USB_BOOT;
176 #ifdef CONFIG_OF_SYSTEM_SETUP
177 int ft_system_setup(void *blob, bd_t *bd)
183 /* Disable the CPU idle for A0 chip since the HW does not support it */
184 if (is_soc_rev(CHIP_REV_1_0)) {
185 static const char * const nodes_path[] = {
192 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
193 nodeoff = fdt_path_offset(blob, nodes_path[i]);
195 continue; /* Not found, skip it */
197 printf("Found %s node\n", nodes_path[i]);
199 rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
201 printf("Unable to update property %s:%s, err=%s\n",
202 nodes_path[i], "status", fdt_strerror(rc));
206 printf("Remove %s:%s\n", nodes_path[i],
215 void reset_cpu(ulong addr)
217 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
219 /* Clear WDA to trigger WDOG_B immediately */
220 writew((WCR_WDE | WCR_SRS), &wdog->wcr);
224 * spin for .5 seconds before reset