4 * Peng Fan <peng.fan@nxp.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/sys_proto.h>
15 #include <linux/iopoll.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
21 static u32 decode_frac_pll(enum clk_root_src frac_pll)
23 u32 pll_cfg0, pll_cfg1, pllout;
24 u32 pll_refclk_sel, pll_refclk;
25 u32 divr_val, divq_val, divf_val, divff, divfi;
26 u32 pllout_div_shift, pllout_div_mask, pllout_div;
30 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
31 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
32 pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
33 pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
36 printf("Frac PLL %d not supporte\n", frac_pll);
40 pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
41 pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
44 if (pll_cfg0 & FRAC_PLL_PD_MASK)
47 /* output not enabled */
48 if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
51 pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
53 if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
54 pll_refclk = 25000000u;
55 else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
56 pll_refclk = 27000000u;
57 else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
58 pll_refclk = 27000000u;
62 if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
65 divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
66 FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
67 divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
69 divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
70 FRAC_PLL_FRAC_DIV_CTL_SHIFT;
71 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
73 divf_val = 1 + divfi + divff / (1 << 24);
75 pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
78 return pllout / (pllout_div + 1);
81 static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
83 u32 pll_cfg0, pll_cfg1, pll_cfg2;
84 u32 pll_refclk_sel, pll_refclk;
85 u32 divr1, divr2, divf1, divf2, divq, div;
88 u32 pllout_div_shift, pllout_div_mask, pllout_div;
92 case SYSTEM_PLL1_800M_CLK:
93 case SYSTEM_PLL1_400M_CLK:
94 case SYSTEM_PLL1_266M_CLK:
95 case SYSTEM_PLL1_200M_CLK:
96 case SYSTEM_PLL1_160M_CLK:
97 case SYSTEM_PLL1_133M_CLK:
98 case SYSTEM_PLL1_100M_CLK:
99 case SYSTEM_PLL1_80M_CLK:
100 case SYSTEM_PLL1_40M_CLK:
101 pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
102 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
103 pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
104 pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
105 pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
107 case SYSTEM_PLL2_1000M_CLK:
108 case SYSTEM_PLL2_500M_CLK:
109 case SYSTEM_PLL2_333M_CLK:
110 case SYSTEM_PLL2_250M_CLK:
111 case SYSTEM_PLL2_200M_CLK:
112 case SYSTEM_PLL2_166M_CLK:
113 case SYSTEM_PLL2_125M_CLK:
114 case SYSTEM_PLL2_100M_CLK:
115 case SYSTEM_PLL2_50M_CLK:
116 pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
117 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
118 pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
119 pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
120 pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
122 case SYSTEM_PLL3_CLK:
123 pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
124 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
125 pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
126 pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
127 pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
130 pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
131 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
132 pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
133 pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
134 pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
137 printf("sscg pll %d not supporte\n", sscg_pll);
143 pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
146 case SYSTEM_PLL3_CLK:
147 pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
150 case SYSTEM_PLL2_1000M_CLK:
151 case SYSTEM_PLL1_800M_CLK:
152 pll_clke = SSCG_PLL_CLKE_MASK;
155 case SYSTEM_PLL2_500M_CLK:
156 case SYSTEM_PLL1_400M_CLK:
157 pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
160 case SYSTEM_PLL2_333M_CLK:
161 case SYSTEM_PLL1_266M_CLK:
162 pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
165 case SYSTEM_PLL2_250M_CLK:
166 case SYSTEM_PLL1_200M_CLK:
167 pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
170 case SYSTEM_PLL2_200M_CLK:
171 case SYSTEM_PLL1_160M_CLK:
172 pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
175 case SYSTEM_PLL2_166M_CLK:
176 case SYSTEM_PLL1_133M_CLK:
177 pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
180 case SYSTEM_PLL2_125M_CLK:
181 case SYSTEM_PLL1_100M_CLK:
182 pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
185 case SYSTEM_PLL2_100M_CLK:
186 case SYSTEM_PLL1_80M_CLK:
187 pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
190 case SYSTEM_PLL2_50M_CLK:
191 case SYSTEM_PLL1_40M_CLK:
192 pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
196 printf("sscg pll %d not supporte\n", sscg_pll);
201 if (pll_cfg0 & SSCG_PLL_PD_MASK)
204 /* output not enabled */
205 if ((pll_cfg0 & pll_clke) == 0)
208 pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
209 pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
211 pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
213 if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
214 pll_refclk = 25000000u;
215 else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
216 pll_refclk = 27000000u;
217 else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
218 pll_refclk = 27000000u;
222 /* We assume bypass1/2 are the same value */
223 if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
224 (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
227 divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
228 SSCG_PLL_REF_DIVR1_SHIFT;
229 divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
230 SSCG_PLL_REF_DIVR2_SHIFT;
231 divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
232 SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
233 divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
234 SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
235 divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
236 SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
237 sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
244 pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
245 (divr2 + 1) * (divf2 + 1) / (divq + 1);
247 return pllout / (pllout_div + 1) / div;
250 static u32 get_root_src_clk(enum clk_root_src root_src)
260 return decode_frac_pll(root_src);
261 case SYSTEM_PLL1_800M_CLK:
262 case SYSTEM_PLL1_400M_CLK:
263 case SYSTEM_PLL1_266M_CLK:
264 case SYSTEM_PLL1_200M_CLK:
265 case SYSTEM_PLL1_160M_CLK:
266 case SYSTEM_PLL1_133M_CLK:
267 case SYSTEM_PLL1_100M_CLK:
268 case SYSTEM_PLL1_80M_CLK:
269 case SYSTEM_PLL1_40M_CLK:
270 case SYSTEM_PLL2_1000M_CLK:
271 case SYSTEM_PLL2_500M_CLK:
272 case SYSTEM_PLL2_333M_CLK:
273 case SYSTEM_PLL2_250M_CLK:
274 case SYSTEM_PLL2_200M_CLK:
275 case SYSTEM_PLL2_166M_CLK:
276 case SYSTEM_PLL2_125M_CLK:
277 case SYSTEM_PLL2_100M_CLK:
278 case SYSTEM_PLL2_50M_CLK:
279 case SYSTEM_PLL3_CLK:
280 return decode_sscg_pll(root_src);
288 static u32 get_root_clk(enum clk_root_index clock_id)
290 enum clk_root_src root_src;
291 u32 post_podf, pre_podf, root_src_clk;
293 if (clock_root_enabled(clock_id) <= 0)
296 if (clock_get_prediv(clock_id, &pre_podf) < 0)
299 if (clock_get_postdiv(clock_id, &post_podf) < 0)
302 if (clock_get_src(clock_id, &root_src) < 0)
305 root_src_clk = get_root_src_clk(root_src);
307 return root_src_clk / (post_podf + 1) / (pre_podf + 1);
310 #ifdef CONFIG_MXC_OCOTP
311 void enable_ocotp_clk(unsigned char enable)
313 clock_enable(CCGR_OCOTP, !!enable);
317 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
319 /* 0 - 3 is valid i2c num */
323 clock_enable(CCGR_I2C1 + i2c_num, !!enable);
328 unsigned int mxc_get_clock(enum clk_root_index clk)
332 if (clk >= CLK_ROOT_MAX)
335 if (clk == MXC_ARM_CLK)
336 return get_root_clk(ARM_A53_CLK_ROOT);
338 if (clk == MXC_IPG_CLK) {
339 clock_get_target_val(IPG_CLK_ROOT, &val);
341 return get_root_clk(AHB_CLK_ROOT) / (val + 1);
344 return get_root_clk(clk);
347 u32 imx_get_uartclk(void)
349 return mxc_get_clock(UART1_CLK_ROOT);
352 void mxs_set_lcdclk(u32 base_addr, u32 freq)
355 * LCDIF_PIXEL_CLK: select 800MHz root clock,
356 * select pre divider 8, output is 100 MHz
358 clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
359 CLK_ROOT_SOURCE_SEL(4) |
360 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
363 void init_wdog_clk(void)
365 clock_enable(CCGR_WDOG1, 0);
366 clock_enable(CCGR_WDOG2, 0);
367 clock_enable(CCGR_WDOG3, 0);
368 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
369 CLK_ROOT_SOURCE_SEL(0));
370 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
371 CLK_ROOT_SOURCE_SEL(0));
372 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
373 CLK_ROOT_SOURCE_SEL(0));
374 clock_enable(CCGR_WDOG1, 1);
375 clock_enable(CCGR_WDOG2, 1);
376 clock_enable(CCGR_WDOG3, 1);
379 void init_usb_clk(void)
381 if (!is_usb_boot()) {
382 clock_enable(CCGR_USB_CTRL1, 0);
383 clock_enable(CCGR_USB_CTRL2, 0);
384 clock_enable(CCGR_USB_PHY1, 0);
385 clock_enable(CCGR_USB_PHY2, 0);
387 clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
388 CLK_ROOT_SOURCE_SEL(1));
390 clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
391 CLK_ROOT_SOURCE_SEL(1));
393 clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
394 CLK_ROOT_SOURCE_SEL(1));
395 clock_enable(CCGR_USB_CTRL1, 1);
396 clock_enable(CCGR_USB_CTRL2, 1);
397 clock_enable(CCGR_USB_PHY1, 1);
398 clock_enable(CCGR_USB_PHY2, 1);
402 void init_uart_clk(u32 index)
404 /* Set uart clock root 25M OSC */
407 clock_enable(CCGR_UART1, 0);
408 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
409 CLK_ROOT_SOURCE_SEL(0));
410 clock_enable(CCGR_UART1, 1);
413 clock_enable(CCGR_UART2, 0);
414 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
415 CLK_ROOT_SOURCE_SEL(0));
416 clock_enable(CCGR_UART2, 1);
419 clock_enable(CCGR_UART3, 0);
420 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
421 CLK_ROOT_SOURCE_SEL(0));
422 clock_enable(CCGR_UART3, 1);
425 clock_enable(CCGR_UART4, 0);
426 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
427 CLK_ROOT_SOURCE_SEL(0));
428 clock_enable(CCGR_UART4, 1);
431 printf("Invalid uart index\n");
436 void init_clk_usdhc(u32 index)
439 * set usdhc clock root
444 clock_enable(CCGR_USDHC1, 0);
445 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
446 CLK_ROOT_SOURCE_SEL(1) |
447 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
448 clock_enable(CCGR_USDHC1, 1);
451 clock_enable(CCGR_USDHC2, 0);
452 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
453 CLK_ROOT_SOURCE_SEL(1) |
454 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
455 clock_enable(CCGR_USDHC2, 1);
458 printf("Invalid usdhc index\n");
463 int set_clk_qspi(void)
469 clock_enable(CCGR_QSPI, 0);
470 clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
471 CLK_ROOT_SOURCE_SEL(7));
472 clock_enable(CCGR_QSPI, 1);
477 #ifdef CONFIG_FEC_MXC
478 int set_clk_enet(enum enet_freq type)
485 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
488 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
491 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
497 /* disable the clock first */
498 clock_enable(CCGR_ENET1, 0);
499 clock_enable(CCGR_SIM_ENET, 0);
501 /* set enet axi clock 266Mhz */
502 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
503 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
504 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
505 clock_set_target_val(ENET_AXI_CLK_ROOT, target);
507 target = CLK_ROOT_ON | enet1_ref |
508 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
509 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
510 clock_set_target_val(ENET_REF_CLK_ROOT, target);
512 target = CLK_ROOT_ON |
513 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
514 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
515 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
516 clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
519 clock_enable(CCGR_SIM_ENET, 1);
520 clock_enable(CCGR_ENET1, 1);
526 u32 imx_get_fecclk(void)
528 return get_root_clk(ENET_AXI_CLK_ROOT);
531 #ifdef CONFIG_SPL_BUILD
532 void dram_pll_init(void)
534 struct src *src = (struct src *)SRC_BASE_ADDR;
535 void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
536 u32 pwdn_mask = 0, pll_clke = 0, bypass1 = 0, bypass2 = 0;
540 setbits_le32(GPC_BASE_ADDR + 0xEC, BIT(7));
541 setbits_le32(GPC_BASE_ADDR + 0xF8, BIT(5));
543 pwdn_mask = SSCG_PLL_PD_MASK;
544 pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
545 bypass1 = SSCG_PLL_BYPASS1_MASK;
546 bypass2 = SSCG_PLL_BYPASS2_MASK;
548 /* Enable DDR1 and DDR2 domain */
549 writel(SRC_DDR1_ENABLE_MASK, &src->ddr1_rcr);
550 writel(SRC_DDR1_ENABLE_MASK, &src->ddr2_rcr);
552 /* Clear power down bit */
553 clrbits_le32(pll_control_reg, pwdn_mask);
554 /* Eanble ARM_PLL/SYS_PLL */
555 setbits_le32(pll_control_reg, pll_clke);
558 clrbits_le32(pll_control_reg, bypass1);
560 clrbits_le32(pll_control_reg, bypass2);
562 ret = readl_poll_timeout(pll_control_reg, val,
563 val & SSCG_PLL_LOCK_MASK, 1);
565 printf("%s timeout\n", __func__);
568 int frac_pll_init(u32 pll, enum frac_pll_out_val val)
570 void __iomem *pll_cfg0, __iomem *pll_cfg1;
571 u32 val_cfg0, val_cfg1;
576 pll_cfg0 = &ana_pll->arm_pll_cfg0;
577 pll_cfg1 = &ana_pll->arm_pll_cfg1;
579 if (val == FRAC_PLL_OUT_1000M)
580 val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
582 val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
583 val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
584 FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
585 FRAC_PLL_REFCLK_DIV_VAL(4) |
586 FRAC_PLL_OUTPUT_DIV_VAL(0);
592 /* bypass the clock */
593 setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
595 writel(val_cfg1, pll_cfg1);
596 writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
597 val_cfg0 = readl(pll_cfg0);
598 /* unbypass the clock */
599 clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
600 ret = readl_poll_timeout(pll_cfg0, val_cfg0,
601 val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
603 printf("%s timeout\n", __func__);
604 clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
609 int sscg_pll_init(u32 pll)
611 void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;
612 u32 val_cfg0, val_cfg1, val_cfg2, val;
613 u32 bypass1_mask = 0x20, bypass2_mask = 0x10;
617 case ANATOP_SYSTEM_PLL1:
618 pll_cfg0 = &ana_pll->sys_pll1_cfg0;
619 pll_cfg1 = &ana_pll->sys_pll1_cfg1;
620 pll_cfg2 = &ana_pll->sys_pll1_cfg2;
622 val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
623 SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
625 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
626 SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
627 SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
628 SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
629 SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
630 SSCG_PLL_REFCLK_SEL_OSC_25M;
632 case ANATOP_SYSTEM_PLL2:
633 pll_cfg0 = &ana_pll->sys_pll2_cfg0;
634 pll_cfg1 = &ana_pll->sys_pll2_cfg1;
635 pll_cfg2 = &ana_pll->sys_pll2_cfg2;
637 val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
638 SSCG_PLL_FEEDBACK_DIV_F2_VAL(4);
640 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
641 SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
642 SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
643 SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
644 SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
645 SSCG_PLL_REFCLK_SEL_OSC_25M;
647 case ANATOP_SYSTEM_PLL3:
648 pll_cfg0 = &ana_pll->sys_pll3_cfg0;
649 pll_cfg1 = &ana_pll->sys_pll3_cfg1;
650 pll_cfg2 = &ana_pll->sys_pll3_cfg2;
652 val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
653 SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
655 val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
656 SSCG_PLL_REFCLK_SEL_OSC_25M;
663 setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);
665 writel(val_cfg2, pll_cfg2);
666 writel(val_cfg1, pll_cfg1);
667 /*unbypass1 and wait 70us */
668 writel(val_cfg0 | bypass2_mask, pll_cfg1);
672 /* unbypass2 and wait lock */
673 writel(val_cfg0, pll_cfg1);
674 ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1);
676 printf("%s timeout\n", __func__);
685 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
686 CLK_ROOT_SOURCE_SEL(0));
689 * 8MQ only supports two grades: consumer and industrial.
690 * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
692 grade = get_cpu_temp_grade(NULL, NULL);
694 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
695 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
696 CLK_ROOT_SOURCE_SEL(1) |
697 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
699 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M);
700 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
701 CLK_ROOT_SOURCE_SEL(1) |
702 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
705 * According to ANAMIX SPEC
706 * sys pll1 fixed at 800MHz
707 * sys pll2 fixed at 1GHz
708 * Here we only enable the outputs.
710 setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
711 SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
712 SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
713 SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
714 SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
716 setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
717 SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
718 SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
719 SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
720 SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
722 clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
723 CLK_ROOT_SOURCE_SEL(1));
726 clock_enable(CCGR_TSENSOR, 1);
735 #ifndef CONFIG_SPL_BUILD
736 int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
741 freq = decode_frac_pll(ARM_PLL_CLK);
742 printf("ARM_PLL %8d MHz\n", freq / 1000000);
743 freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
744 printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
745 freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
746 printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
747 freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
748 printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
749 freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
750 printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
751 freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
752 printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
753 freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
754 printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
755 freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
756 printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
757 freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
758 printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
759 freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
760 printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
761 freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
762 printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
763 freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
764 printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
765 freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
766 printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
767 freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
768 printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
769 freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
770 printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
771 freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
772 printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
773 freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
774 printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
775 freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
776 printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
777 freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
778 printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
779 freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
780 printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
781 freq = mxc_get_clock(UART1_CLK_ROOT);
782 printf("UART1 %8d MHz\n", freq / 1000000);
783 freq = mxc_get_clock(USDHC1_CLK_ROOT);
784 printf("USDHC1 %8d MHz\n", freq / 1000000);
785 freq = mxc_get_clock(QSPI_CLK_ROOT);
786 printf("QSPI %8d MHz\n", freq / 1000000);
791 clocks, CONFIG_SYS_MAXARGS, 1, do_mx8m_showclocks,