2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/clock.h>
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/mach-imx/hab.h>
12 static char *get_reset_cause(char *);
14 #if defined(CONFIG_SECURE_BOOT)
15 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
23 /* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */
24 return (MXC_CPU_MX7ULP << 12) | (1 << 4);
27 #ifdef CONFIG_REVISION_TAG
28 u32 __weak get_board_rev(void)
34 enum bt_mode get_boot_mode(void)
38 bt0_cfg = readl(CMC0_RBASE + 0x40);
39 bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
41 if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
42 /* No low power boot */
43 if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
49 return LOW_POWER_BOOT;
52 int arch_cpu_init(void)
57 #ifdef CONFIG_BOARD_POSTCLK_INIT
58 int board_postclk_init(void)
64 #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
65 #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
66 #define REFRESH_WORD0 0xA602 /* 1st refresh word */
67 #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
69 static void disable_wdog(u32 wdog_base)
71 writel(UNLOCK_WORD0, (wdog_base + 0x04));
72 writel(UNLOCK_WORD1, (wdog_base + 0x04));
73 writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
74 writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
75 writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
77 writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
78 writel(REFRESH_WORD1, (wdog_base + 0x04));
84 * ROM will configure WDOG1, disable it or enable it
85 * depending on FUSE. The update bit is set for reconfigurable.
86 * We have to use unlock sequence to reconfigure it.
87 * WDOG2 is not touched by ROM, so it will have default value
88 * which is enabled. We can directly configure it.
89 * To simplify the codes, we still use same reconfigure
90 * process as WDOG1. Because the update bit is not set for
91 * WDOG2, the unlock sequence won't take effect really.
92 * It actually directly configure the wdog.
93 * In this function, we will disable both WDOG1 and WDOG2,
94 * and set update bit for both. So that kernel can reconfigure them.
96 disable_wdog(WDG1_RBASE);
97 disable_wdog(WDG2_RBASE);
106 /* clock configuration. */
112 #ifndef CONFIG_ULP_WATCHDOG
113 void reset_cpu(ulong addr)
115 setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
121 #if defined(CONFIG_DISPLAY_CPUINFO)
122 const char *get_imx_type(u32 imxtype)
127 int print_cpuinfo(void)
132 cpurev = get_cpu_rev();
134 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
135 get_imx_type((cpurev & 0xFF000) >> 12),
136 (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
137 mxc_get_clock(MXC_ARM_CLK) / 1000000);
139 printf("Reset cause: %s\n", get_reset_cause(cause));
141 printf("Boot mode: ");
142 switch (get_boot_mode()) {
144 printf("Low power boot\n");
147 printf("Dual boot\n");
151 printf("Single boot\n");
159 #define CMC_SRS_TAMPER (1 << 31)
160 #define CMC_SRS_SECURITY (1 << 30)
161 #define CMC_SRS_TZWDG (1 << 29)
162 #define CMC_SRS_JTAG_RST (1 << 28)
163 #define CMC_SRS_CORE1 (1 << 16)
164 #define CMC_SRS_LOCKUP (1 << 15)
165 #define CMC_SRS_SW (1 << 14)
166 #define CMC_SRS_WDG (1 << 13)
167 #define CMC_SRS_PIN_RESET (1 << 8)
168 #define CMC_SRS_WARM (1 << 4)
169 #define CMC_SRS_HVD (1 << 3)
170 #define CMC_SRS_LVD (1 << 2)
171 #define CMC_SRS_POR (1 << 1)
172 #define CMC_SRS_WUP (1 << 0)
174 static u32 reset_cause = -1;
176 static char *get_reset_cause(char *ret)
178 u32 cause1, cause = 0, srs = 0;
179 u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28);
180 u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20);
185 srs = readl(reg_srs);
186 cause1 = readl(reg_ssrs);
187 writel(cause1, reg_ssrs);
189 reset_cause = cause1;
191 cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
195 sprintf(ret, "%s", "POR");
198 sprintf(ret, "%s", "WUP");
201 cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
205 sprintf(ret, "%s", "WARM-WDG");
208 sprintf(ret, "%s", "WARM-SW");
210 case CMC_SRS_JTAG_RST:
211 sprintf(ret, "%s", "WARM-JTAG");
214 sprintf(ret, "%s", "WARM-UNKN");
219 sprintf(ret, "%s-%X", "UNKN", cause1);
223 debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1);
227 #ifdef CONFIG_ENV_IS_IN_MMC
228 __weak int board_mmc_get_env_dev(int devno)
230 return CONFIG_SYS_MMC_ENV_DEV;
233 int mmc_get_env_dev(void)
238 /* If not boot from sd/mmc, use default value */
239 if (get_boot_mode() == LOW_POWER_BOOT)
240 return CONFIG_SYS_MMC_ENV_DEV;
242 bt1_cfg = readl(CMC1_RBASE + 0x40);
243 devno = (bt1_cfg >> 9) & 0x7;
245 return board_mmc_get_env_dev(devno);