2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/pcc.h>
13 #include <asm/arch/sys_proto.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 scg_p scg1_regs = (scg_p)SCG1_RBASE;
19 static u32 scg_src_get_rate(enum scg_clk clksrc)
25 reg = readl(&scg1_regs->sosccsr);
26 if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK))
31 reg = readl(&scg1_regs->firccsr);
32 if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK))
37 reg = readl(&scg1_regs->sirccsr);
38 if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK))
43 reg = readl(&scg1_regs->rtccsr);
44 if (!(reg & SCG_ROSC_CSR_ROSCVLD_MASK))
55 static u32 scg_sircdiv_get_rate(enum scg_clk clk)
61 case SCG_SIRC_DIV1_CLK:
62 mask = SCG_SIRCDIV_DIV1_MASK;
63 shift = SCG_SIRCDIV_DIV1_SHIFT;
65 case SCG_SIRC_DIV2_CLK:
66 mask = SCG_SIRCDIV_DIV2_MASK;
67 shift = SCG_SIRCDIV_DIV2_SHIFT;
69 case SCG_SIRC_DIV3_CLK:
70 mask = SCG_SIRCDIV_DIV3_MASK;
71 shift = SCG_SIRCDIV_DIV3_SHIFT;
77 reg = readl(&scg1_regs->sirccsr);
78 if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK))
81 reg = readl(&scg1_regs->sircdiv);
82 val = (reg & mask) >> shift;
84 if (!val) /*clock disabled*/
87 rate = scg_src_get_rate(SCG_SIRC_CLK);
88 rate = rate / (1 << (val - 1));
93 static u32 scg_fircdiv_get_rate(enum scg_clk clk)
99 case SCG_FIRC_DIV1_CLK:
100 mask = SCG_FIRCDIV_DIV1_MASK;
101 shift = SCG_FIRCDIV_DIV1_SHIFT;
103 case SCG_FIRC_DIV2_CLK:
104 mask = SCG_FIRCDIV_DIV2_MASK;
105 shift = SCG_FIRCDIV_DIV2_SHIFT;
107 case SCG_FIRC_DIV3_CLK:
108 mask = SCG_FIRCDIV_DIV3_MASK;
109 shift = SCG_FIRCDIV_DIV3_SHIFT;
115 reg = readl(&scg1_regs->firccsr);
116 if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK))
119 reg = readl(&scg1_regs->fircdiv);
120 val = (reg & mask) >> shift;
122 if (!val) /*clock disabled*/
125 rate = scg_src_get_rate(SCG_FIRC_CLK);
126 rate = rate / (1 << (val - 1));
131 static u32 scg_soscdiv_get_rate(enum scg_clk clk)
137 case SCG_SOSC_DIV1_CLK:
138 mask = SCG_SOSCDIV_DIV1_MASK;
139 shift = SCG_SOSCDIV_DIV1_SHIFT;
141 case SCG_SOSC_DIV2_CLK:
142 mask = SCG_SOSCDIV_DIV2_MASK;
143 shift = SCG_SOSCDIV_DIV2_SHIFT;
145 case SCG_SOSC_DIV3_CLK:
146 mask = SCG_SOSCDIV_DIV3_MASK;
147 shift = SCG_SOSCDIV_DIV3_SHIFT;
153 reg = readl(&scg1_regs->sosccsr);
154 if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK))
157 reg = readl(&scg1_regs->soscdiv);
158 val = (reg & mask) >> shift;
160 if (!val) /*clock disabled*/
163 rate = scg_src_get_rate(SCG_SOSC_CLK);
164 rate = rate / (1 << (val - 1));
169 static u32 scg_apll_pfd_get_rate(enum scg_clk clk)
172 u32 shift, mask, gate, valid;
175 case SCG_APLL_PFD0_CLK:
176 gate = SCG_PLL_PFD0_GATE_MASK;
177 valid = SCG_PLL_PFD0_VALID_MASK;
178 mask = SCG_PLL_PFD0_FRAC_MASK;
179 shift = SCG_PLL_PFD0_FRAC_SHIFT;
181 case SCG_APLL_PFD1_CLK:
182 gate = SCG_PLL_PFD1_GATE_MASK;
183 valid = SCG_PLL_PFD1_VALID_MASK;
184 mask = SCG_PLL_PFD1_FRAC_MASK;
185 shift = SCG_PLL_PFD1_FRAC_SHIFT;
187 case SCG_APLL_PFD2_CLK:
188 gate = SCG_PLL_PFD2_GATE_MASK;
189 valid = SCG_PLL_PFD2_VALID_MASK;
190 mask = SCG_PLL_PFD2_FRAC_MASK;
191 shift = SCG_PLL_PFD2_FRAC_SHIFT;
193 case SCG_APLL_PFD3_CLK:
194 gate = SCG_PLL_PFD3_GATE_MASK;
195 valid = SCG_PLL_PFD3_VALID_MASK;
196 mask = SCG_PLL_PFD3_FRAC_MASK;
197 shift = SCG_PLL_PFD3_FRAC_SHIFT;
203 reg = readl(&scg1_regs->apllpfd);
204 if (reg & gate || !(reg & valid))
207 clk_debug("scg_apll_pfd_get_rate reg 0x%x\n", reg);
209 val = (reg & mask) >> shift;
210 rate = decode_pll(PLL_A7_APLL);
212 rate = rate / val * 18;
214 clk_debug("scg_apll_pfd_get_rate rate %u\n", rate);
219 static u32 scg_spll_pfd_get_rate(enum scg_clk clk)
222 u32 shift, mask, gate, valid;
225 case SCG_SPLL_PFD0_CLK:
226 gate = SCG_PLL_PFD0_GATE_MASK;
227 valid = SCG_PLL_PFD0_VALID_MASK;
228 mask = SCG_PLL_PFD0_FRAC_MASK;
229 shift = SCG_PLL_PFD0_FRAC_SHIFT;
231 case SCG_SPLL_PFD1_CLK:
232 gate = SCG_PLL_PFD1_GATE_MASK;
233 valid = SCG_PLL_PFD1_VALID_MASK;
234 mask = SCG_PLL_PFD1_FRAC_MASK;
235 shift = SCG_PLL_PFD1_FRAC_SHIFT;
237 case SCG_SPLL_PFD2_CLK:
238 gate = SCG_PLL_PFD2_GATE_MASK;
239 valid = SCG_PLL_PFD2_VALID_MASK;
240 mask = SCG_PLL_PFD2_FRAC_MASK;
241 shift = SCG_PLL_PFD2_FRAC_SHIFT;
243 case SCG_SPLL_PFD3_CLK:
244 gate = SCG_PLL_PFD3_GATE_MASK;
245 valid = SCG_PLL_PFD3_VALID_MASK;
246 mask = SCG_PLL_PFD3_FRAC_MASK;
247 shift = SCG_PLL_PFD3_FRAC_SHIFT;
253 reg = readl(&scg1_regs->spllpfd);
254 if (reg & gate || !(reg & valid))
257 clk_debug("scg_spll_pfd_get_rate reg 0x%x\n", reg);
259 val = (reg & mask) >> shift;
260 rate = decode_pll(PLL_A7_SPLL);
262 rate = rate / val * 18;
264 clk_debug("scg_spll_pfd_get_rate rate %u\n", rate);
269 static u32 scg_apll_get_rate(void)
273 reg = readl(&scg1_regs->apllcfg);
274 val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT;
277 /* APLL clock after two dividers */
278 rate = decode_pll(PLL_A7_APLL);
280 val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >>
281 SCG_PLL_CFG_POSTDIV1_SHIFT;
282 rate = rate / (val + 1);
284 val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >>
285 SCG_PLL_CFG_POSTDIV2_SHIFT;
286 rate = rate / (val + 1);
289 val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
290 SCG_PLL_CFG_PFDSEL_SHIFT;
291 rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val);
297 static u32 scg_spll_get_rate(void)
301 reg = readl(&scg1_regs->spllcfg);
302 val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT;
304 clk_debug("scg_spll_get_rate reg 0x%x\n", reg);
307 /* APLL clock after two dividers */
308 rate = decode_pll(PLL_A7_SPLL);
310 val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >>
311 SCG_PLL_CFG_POSTDIV1_SHIFT;
312 rate = rate / (val + 1);
314 val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >>
315 SCG_PLL_CFG_POSTDIV2_SHIFT;
316 rate = rate / (val + 1);
318 clk_debug("scg_spll_get_rate SPLL %u\n", rate);
322 val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
323 SCG_PLL_CFG_PFDSEL_SHIFT;
324 rate = scg_spll_pfd_get_rate(SCG_SPLL_PFD0_CLK + val);
326 clk_debug("scg_spll_get_rate PFD %u\n", rate);
332 static u32 scg_ddr_get_rate(void)
334 u32 reg, val, rate, div;
336 reg = readl(&scg1_regs->ddrccr);
337 val = (reg & SCG_DDRCCR_DDRCS_MASK) >> SCG_DDRCCR_DDRCS_SHIFT;
338 div = (reg & SCG_DDRCCR_DDRDIV_MASK) >> SCG_DDRCCR_DDRDIV_SHIFT;
344 reg = readl(&scg1_regs->apllcfg);
345 val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
346 SCG_PLL_CFG_PFDSEL_SHIFT;
347 rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val);
349 rate = decode_pll(PLL_USB);
352 rate = rate / (1 << (div - 1));
356 static u32 scg_nic_get_rate(enum scg_clk clk)
361 reg = readl(&scg1_regs->niccsr);
362 val = (reg & SCG_NICCSR_NICCS_MASK) >> SCG_NICCSR_NICCS_SHIFT;
364 clk_debug("scg_nic_get_rate niccsr 0x%x\n", reg);
367 rate = scg_src_get_rate(SCG_FIRC_CLK);
369 rate = scg_ddr_get_rate();
371 clk_debug("scg_nic_get_rate parent rate %u\n", rate);
373 val = (reg & SCG_NICCSR_NIC0DIV_MASK) >> SCG_NICCSR_NIC0DIV_SHIFT;
375 rate = rate / (val + 1);
377 clk_debug("scg_nic_get_rate NIC0 rate %u\n", rate);
383 mask = SCG_NICCSR_GPUDIV_MASK;
384 shift = SCG_NICCSR_GPUDIV_SHIFT;
386 case SCG_NIC1_EXT_CLK:
387 case SCG_NIC1_BUS_CLK:
389 mask = SCG_NICCSR_NIC1DIV_MASK;
390 shift = SCG_NICCSR_NIC1DIV_SHIFT;
396 val = (reg & mask) >> shift;
397 rate = rate / (val + 1);
399 clk_debug("scg_nic_get_rate NIC1 rate %u\n", rate);
405 case SCG_NIC1_EXT_CLK:
406 mask = SCG_NICCSR_NIC1EXTDIV_MASK;
407 shift = SCG_NICCSR_NIC1EXTDIV_SHIFT;
409 case SCG_NIC1_BUS_CLK:
410 mask = SCG_NICCSR_NIC1BUSDIV_MASK;
411 shift = SCG_NICCSR_NIC1BUSDIV_SHIFT;
417 val = (reg & mask) >> shift;
418 rate = rate / (val + 1);
420 clk_debug("scg_nic_get_rate NIC1 bus rate %u\n", rate);
425 static enum scg_clk scg_scs_array[4] = {
426 SCG_SOSC_CLK, SCG_SIRC_CLK, SCG_FIRC_CLK, SCG_ROSC_CLK,
429 static u32 scg_sys_get_rate(enum scg_clk clk)
433 if (clk != SCG_CORE_CLK && clk != SCG_BUS_CLK)
436 reg = readl(&scg1_regs->csr);
437 val = (reg & SCG_CCR_SCS_MASK) >> SCG_CCR_SCS_SHIFT;
439 clk_debug("scg_sys_get_rate reg 0x%x\n", reg);
442 case SCG_SCS_SYS_OSC:
443 case SCG_SCS_SLOW_IRC:
444 case SCG_SCS_FAST_IRC:
445 case SCG_SCS_RTC_OSC:
446 rate = scg_src_get_rate(scg_scs_array[val]);
449 rate = scg_apll_get_rate();
452 rate = scg_spll_get_rate();
458 clk_debug("scg_sys_get_rate parent rate %u\n", rate);
460 val = (reg & SCG_CCR_DIVCORE_MASK) >> SCG_CCR_DIVCORE_SHIFT;
462 rate = rate / (val + 1);
464 if (clk == SCG_BUS_CLK) {
465 val = (reg & SCG_CCR_DIVBUS_MASK) >> SCG_CCR_DIVBUS_SHIFT;
466 rate = rate / (val + 1);
472 u32 decode_pll(enum pll_clocks pll)
474 u32 reg, pre_div, infreq, mult;
478 * Alought there are four choices for the bypass src,
479 * we choose OSC_24M which is the default set in ROM.
483 reg = readl(&scg1_regs->spllcsr);
485 if (!(reg & SCG_SPLL_CSR_SPLLVLD_MASK))
488 reg = readl(&scg1_regs->spllcfg);
490 pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >>
491 SCG_PLL_CFG_PREDIV_SHIFT;
494 mult = (reg & SCG1_SPLL_CFG_MULT_MASK) >>
495 SCG_PLL_CFG_MULT_SHIFT;
497 infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >>
498 SCG_PLL_CFG_CLKSRC_SHIFT;
500 infreq = scg_src_get_rate(SCG_SOSC_CLK);
502 infreq = scg_src_get_rate(SCG_FIRC_CLK);
504 num = readl(&scg1_regs->spllnum);
505 denom = readl(&scg1_regs->splldenom);
507 infreq = infreq / pre_div;
509 return infreq * mult + infreq * num / denom;
512 reg = readl(&scg1_regs->apllcsr);
514 if (!(reg & SCG_APLL_CSR_APLLVLD_MASK))
517 reg = readl(&scg1_regs->apllcfg);
519 pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >>
520 SCG_PLL_CFG_PREDIV_SHIFT;
523 mult = (reg & SCG_APLL_CFG_MULT_MASK) >>
524 SCG_PLL_CFG_MULT_SHIFT;
526 infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >>
527 SCG_PLL_CFG_CLKSRC_SHIFT;
529 infreq = scg_src_get_rate(SCG_SOSC_CLK);
531 infreq = scg_src_get_rate(SCG_FIRC_CLK);
533 num = readl(&scg1_regs->apllnum);
534 denom = readl(&scg1_regs->aplldenom);
536 infreq = infreq / pre_div;
538 return infreq * mult + infreq * num / denom;
541 reg = readl(&scg1_regs->upllcsr);
543 if (!(reg & SCG_UPLL_CSR_UPLLVLD_MASK))
551 printf("Unsupported pll clocks %d\n", pll);
558 u32 scg_clk_get_rate(enum scg_clk clk)
561 case SCG_SIRC_DIV1_CLK:
562 case SCG_SIRC_DIV2_CLK:
563 case SCG_SIRC_DIV3_CLK:
564 return scg_sircdiv_get_rate(clk);
566 case SCG_FIRC_DIV1_CLK:
567 case SCG_FIRC_DIV2_CLK:
568 case SCG_FIRC_DIV3_CLK:
569 return scg_fircdiv_get_rate(clk);
571 case SCG_SOSC_DIV1_CLK:
572 case SCG_SOSC_DIV2_CLK:
573 case SCG_SOSC_DIV3_CLK:
574 return scg_soscdiv_get_rate(clk);
578 return scg_sys_get_rate(clk);
580 case SCG_SPLL_PFD0_CLK:
581 case SCG_SPLL_PFD1_CLK:
582 case SCG_SPLL_PFD2_CLK:
583 case SCG_SPLL_PFD3_CLK:
584 return scg_spll_pfd_get_rate(clk);
586 case SCG_APLL_PFD0_CLK:
587 case SCG_APLL_PFD1_CLK:
588 case SCG_APLL_PFD2_CLK:
589 case SCG_APLL_PFD3_CLK:
590 return scg_apll_pfd_get_rate(clk);
593 return scg_ddr_get_rate();
598 case SCG_NIC1_BUS_CLK:
599 case SCG_NIC1_EXT_CLK:
600 return scg_nic_get_rate(clk);
603 return decode_pll(PLL_USB);
606 return decode_pll(PLL_MIPI);
612 return scg_src_get_rate(clk);
618 int scg_enable_pll_pfd(enum scg_clk clk, u32 frac)
621 u32 shift, mask, gate, valid;
624 if (frac < 12 || frac > 35)
628 case SCG_SPLL_PFD0_CLK:
629 case SCG_APLL_PFD0_CLK:
630 gate = SCG_PLL_PFD0_GATE_MASK;
631 valid = SCG_PLL_PFD0_VALID_MASK;
632 mask = SCG_PLL_PFD0_FRAC_MASK;
633 shift = SCG_PLL_PFD0_FRAC_SHIFT;
635 if (clk == SCG_SPLL_PFD0_CLK)
636 addr = (u32)(&scg1_regs->spllpfd);
638 addr = (u32)(&scg1_regs->apllpfd);
640 case SCG_SPLL_PFD1_CLK:
641 case SCG_APLL_PFD1_CLK:
642 gate = SCG_PLL_PFD1_GATE_MASK;
643 valid = SCG_PLL_PFD1_VALID_MASK;
644 mask = SCG_PLL_PFD1_FRAC_MASK;
645 shift = SCG_PLL_PFD1_FRAC_SHIFT;
647 if (clk == SCG_SPLL_PFD1_CLK)
648 addr = (u32)(&scg1_regs->spllpfd);
650 addr = (u32)(&scg1_regs->apllpfd);
652 case SCG_SPLL_PFD2_CLK:
653 case SCG_APLL_PFD2_CLK:
654 gate = SCG_PLL_PFD2_GATE_MASK;
655 valid = SCG_PLL_PFD2_VALID_MASK;
656 mask = SCG_PLL_PFD2_FRAC_MASK;
657 shift = SCG_PLL_PFD2_FRAC_SHIFT;
659 if (clk == SCG_SPLL_PFD2_CLK)
660 addr = (u32)(&scg1_regs->spllpfd);
662 addr = (u32)(&scg1_regs->apllpfd);
664 case SCG_SPLL_PFD3_CLK:
665 case SCG_APLL_PFD3_CLK:
666 gate = SCG_PLL_PFD3_GATE_MASK;
667 valid = SCG_PLL_PFD3_VALID_MASK;
668 mask = SCG_PLL_PFD3_FRAC_MASK;
669 shift = SCG_PLL_PFD3_FRAC_SHIFT;
671 if (clk == SCG_SPLL_PFD3_CLK)
672 addr = (u32)(&scg1_regs->spllpfd);
674 addr = (u32)(&scg1_regs->apllpfd);
685 /* Write Frac divider */
687 reg |= (frac << shift) & mask;
692 * (Need un-gate before checking valid, not align with RM)
697 /* Wait for PFD clock being valid */
700 } while (!(reg & valid));
705 #define SIM_MISC_CTRL0_USB_PLL_EN_MASK (0x1 << 2)
706 int scg_enable_usb_pll(bool usb_control)
709 s32 timeout = 1000000;
712 struct usbphy_regs *usbphy =
713 (struct usbphy_regs *)USBPHY_RBASE;
715 sosc_rate = scg_src_get_rate(SCG_SOSC_CLK);
719 reg = readl(SIM0_RBASE + 0x3C);
721 reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK;
723 reg |= SIM_MISC_CTRL0_USB_PLL_EN_MASK;
724 writel(reg, SIM0_RBASE + 0x3C);
726 if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) {
727 writel(0x1c00000, &usbphy->usb1_pll_480_ctrl_clr);
731 writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);
735 writel(0x800000, &usbphy->usb1_pll_480_ctrl_set);
739 writel(0x1400000, &usbphy->usb1_pll_480_ctrl_set);
743 writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);
747 /* Enable the regulator first */
748 writel(PLL_USB_REG_ENABLE_MASK,
749 &usbphy->usb1_pll_480_ctrl_set);
751 /* Wait at least 15us */
754 /* Enable the power */
755 writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set);
759 if (readl(&usbphy->usb1_pll_480_ctrl) &
765 /* If timeout, we power down the pll */
766 writel(PLL_USB_PWR_MASK,
767 &usbphy->usb1_pll_480_ctrl_clr);
772 /* Clear the bypass */
773 writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr);
775 /* Enable the PLL clock out to USB */
776 writel((PLL_USB_EN_USB_CLKS_MASK | PLL_USB_ENABLE_MASK),
777 &usbphy->usb1_pll_480_ctrl_set);
781 if (readl(&scg1_regs->upllcsr) &
782 SCG_UPLL_CSR_UPLLVLD_MASK)
787 reg = readl(SIM0_RBASE + 0x3C);
788 reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK;
789 writel(reg, SIM0_RBASE + 0x3C);
798 /* A7 domain system clock source is SPLL */
799 #define SCG1_RCCR_SCS_NUM ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT)
801 /* A7 Core clck = SPLL PFD0 / 1 = 500MHz / 1 = 500MHz */
802 #define SCG1_RCCR_DIVCORE_NUM ((0x0) << SCG_CCR_DIVCORE_SHIFT)
803 #define SCG1_RCCR_CFG_MASK (SCG_CCR_SCS_MASK | SCG_CCR_DIVBUS_MASK)
805 /* A7 Plat clck = A7 Core Clock / 2 = 250MHz / 1 = 250MHz */
806 #define SCG1_RCCR_DIVBUS_NUM ((0x1) << SCG_CCR_DIVBUS_SHIFT)
807 #define SCG1_RCCR_CFG_NUM (SCG1_RCCR_SCS_NUM | SCG1_RCCR_DIVBUS_NUM)
809 void scg_a7_rccr_init(void)
811 u32 rccr_reg_val = 0;
813 rccr_reg_val = readl(&scg1_regs->rccr);
815 rccr_reg_val &= (~SCG1_RCCR_CFG_MASK);
816 rccr_reg_val |= (SCG1_RCCR_CFG_NUM);
818 writel(rccr_reg_val, &scg1_regs->rccr);
822 #define SCG1_SPLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT)
824 #define SCG1_SPLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT)
827 #define SCG1_SPLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT)
829 /* PFD0 output clock selected */
830 #define SCG1_SPLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT)
832 #define SCG1_SPLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT)
833 /* SPLL output clocks (including PFD outputs) selected */
834 #define SCG1_SPLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT)
835 /* SPLL PFD output clock selected */
836 #define SCG1_SPLL_CFG_PLLSEL_NUM ((0x1) << SCG_PLL_CFG_PLLSEL_SHIFT)
837 /* Clock source is System OSC */
838 #define SCG1_SPLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
839 #define SCG1_SPLL_CFG_NUM_24M_OSC (SCG1_SPLL_CFG_POSTDIV2_NUM | \
840 SCG1_SPLL_CFG_POSTDIV1_NUM | \
841 (22 << SCG_PLL_CFG_MULT_SHIFT) | \
842 SCG1_SPLL_CFG_PFDSEL_NUM | \
843 SCG1_SPLL_CFG_PREDIV_NUM | \
844 SCG1_SPLL_CFG_BYPASS_NUM | \
845 SCG1_SPLL_CFG_PLLSEL_NUM | \
846 SCG1_SPLL_CFG_CLKSRC_NUM)
847 /*413Mhz = A7 SPLL(528MHz) * 18/23 */
848 #define SCG1_SPLL_PFD0_FRAC_NUM ((23) << SCG_PLL_PFD0_FRAC_SHIFT)
850 void scg_a7_spll_init(void)
854 /* Disable A7 System PLL */
855 val = readl(&scg1_regs->spllcsr);
856 val &= ~SCG_SPLL_CSR_SPLLEN_MASK;
857 writel(val, &scg1_regs->spllcsr);
861 * "When changing PFD values, it is recommneded PFDx clock
862 * gets gated first by writing a value of 1 to PFDx_CLKGATE register,
863 * then program the new PFD value, then poll the PFDx_VALID
864 * flag to set before writing a value of 0 to PFDx_CLKGATE
865 * to ungate the PFDx clock and allow PFDx clock to run"
868 /* Gate off A7 SPLL PFD0 ~ PDF4 */
869 val = readl(&scg1_regs->spllpfd);
870 val |= (SCG_PLL_PFD3_GATE_MASK |
871 SCG_PLL_PFD2_GATE_MASK |
872 SCG_PLL_PFD1_GATE_MASK |
873 SCG_PLL_PFD0_GATE_MASK);
874 writel(val, &scg1_regs->spllpfd);
876 /* ================ A7 SPLL Configuration Start ============== */
878 /* Configure A7 System PLL */
879 writel(SCG1_SPLL_CFG_NUM_24M_OSC, &scg1_regs->spllcfg);
881 /* Enable A7 System PLL */
882 val = readl(&scg1_regs->spllcsr);
883 val |= SCG_SPLL_CSR_SPLLEN_MASK;
884 writel(val, &scg1_regs->spllcsr);
886 /* Wait for A7 SPLL clock ready */
887 while (!(readl(&scg1_regs->spllcsr) & SCG_SPLL_CSR_SPLLVLD_MASK))
890 /* Configure A7 SPLL PFD0 */
891 val = readl(&scg1_regs->spllpfd);
892 val &= ~SCG_PLL_PFD0_FRAC_MASK;
893 val |= SCG1_SPLL_PFD0_FRAC_NUM;
894 writel(val, &scg1_regs->spllpfd);
896 /* Un-gate A7 SPLL PFD0 */
897 val = readl(&scg1_regs->spllpfd);
898 val &= ~SCG_PLL_PFD0_GATE_MASK;
899 writel(val, &scg1_regs->spllpfd);
901 /* Wait for A7 SPLL PFD0 clock being valid */
902 while (!(readl(&scg1_regs->spllpfd) & SCG_PLL_PFD0_VALID_MASK))
905 /* ================ A7 SPLL Configuration End ============== */
908 /* DDR clock source is APLL PFD0 (396MHz) */
909 #define SCG1_DDRCCR_DDRCS_NUM ((0x0) << SCG_DDRCCR_DDRCS_SHIFT)
910 /* DDR clock = APLL PFD0 / 1 = 396MHz / 1 = 396MHz */
911 #define SCG1_DDRCCR_DDRDIV_NUM ((0x1) << SCG_DDRCCR_DDRDIV_SHIFT)
912 /* DDR clock = APLL PFD0 / 2 = 396MHz / 2 = 198MHz */
913 #define SCG1_DDRCCR_DDRDIV_LF_NUM ((0x2) << SCG_DDRCCR_DDRDIV_SHIFT)
914 #define SCG1_DDRCCR_CFG_NUM (SCG1_DDRCCR_DDRCS_NUM | \
915 SCG1_DDRCCR_DDRDIV_NUM)
916 #define SCG1_DDRCCR_CFG_LF_NUM (SCG1_DDRCCR_DDRCS_NUM | \
917 SCG1_DDRCCR_DDRDIV_LF_NUM)
918 void scg_a7_ddrclk_init(void)
920 writel(SCG1_DDRCCR_CFG_NUM, &scg1_regs->ddrccr);
923 /* SCG1(A7) APLLCFG configurations */
924 /* divide by 1 <<28 */
925 #define SCG1_APLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT)
926 /* divide by 1 <<24 */
927 #define SCG1_APLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT)
928 /* MULT is 22 <<16 */
929 #define SCG1_APLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT)
930 /* PFD0 output clock selected <<14 */
931 #define SCG1_APLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT)
933 #define SCG1_APLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT)
934 /* APLL output clocks (including PFD outputs) selected <<2 */
935 #define SCG1_APLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT)
936 /* APLL PFD output clock selected <<1 */
937 #define SCG1_APLL_CFG_PLLSEL_NUM ((0x0) << SCG_PLL_CFG_PLLSEL_SHIFT)
938 /* Clock source is System OSC <<0 */
939 #define SCG1_APLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
942 * A7 APLL = 24MHz / 1 * 22 / 1 / 1 = 528MHz,
943 * system PLL is sourced from APLL,
944 * APLL clock source is system OSC (24MHz)
946 #define SCG1_APLL_CFG_NUM_24M_OSC (SCG1_APLL_CFG_POSTDIV2_NUM | \
947 SCG1_APLL_CFG_POSTDIV1_NUM | \
948 (22 << SCG_PLL_CFG_MULT_SHIFT) | \
949 SCG1_APLL_CFG_PFDSEL_NUM | \
950 SCG1_APLL_CFG_PREDIV_NUM | \
951 SCG1_APLL_CFG_BYPASS_NUM | \
952 SCG1_APLL_CFG_PLLSEL_NUM | \
953 SCG1_APLL_CFG_CLKSRC_NUM)
955 /* PFD0 Freq = A7 APLL(528MHz) * 18 / 27 = 352MHz */
956 #define SCG1_APLL_PFD0_FRAC_NUM (27)
959 void scg_a7_apll_init(void)
963 /* Disable A7 Auxiliary PLL */
964 val = readl(&scg1_regs->apllcsr);
965 val &= ~SCG_APLL_CSR_APLLEN_MASK;
966 writel(val, &scg1_regs->apllcsr);
968 /* Gate off A7 APLL PFD0 ~ PDF4 */
969 val = readl(&scg1_regs->apllpfd);
971 writel(val, &scg1_regs->apllpfd);
973 /* ================ A7 APLL Configuration Start ============== */
974 /* Configure A7 Auxiliary PLL */
975 writel(SCG1_APLL_CFG_NUM_24M_OSC, &scg1_regs->apllcfg);
977 /* Enable A7 Auxiliary PLL */
978 val = readl(&scg1_regs->apllcsr);
979 val |= SCG_APLL_CSR_APLLEN_MASK;
980 writel(val, &scg1_regs->apllcsr);
982 /* Wait for A7 APLL clock ready */
983 while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK))
986 /* Configure A7 APLL PFD0 */
987 val = readl(&scg1_regs->apllpfd);
988 val &= ~SCG_PLL_PFD0_FRAC_MASK;
989 val |= SCG1_APLL_PFD0_FRAC_NUM;
990 writel(val, &scg1_regs->apllpfd);
992 /* Un-gate A7 APLL PFD0 */
993 val = readl(&scg1_regs->apllpfd);
994 val &= ~SCG_PLL_PFD0_GATE_MASK;
995 writel(val, &scg1_regs->apllpfd);
997 /* Wait for A7 APLL PFD0 clock being valid */
998 while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK))
1002 /* SCG1(A7) FIRC DIV configurations */
1003 /* Disable FIRC DIV3 */
1004 #define SCG1_FIRCDIV_DIV3_NUM ((0x0) << SCG_FIRCDIV_DIV3_SHIFT)
1005 /* FIRC DIV2 = 48MHz / 1 = 48MHz */
1006 #define SCG1_FIRCDIV_DIV2_NUM ((0x1) << SCG_FIRCDIV_DIV2_SHIFT)
1007 /* Disable FIRC DIV1 */
1008 #define SCG1_FIRCDIV_DIV1_NUM ((0x0) << SCG_FIRCDIV_DIV1_SHIFT)
1010 void scg_a7_firc_init(void)
1012 /* Wait for FIRC clock ready */
1013 while (!(readl(&scg1_regs->firccsr) & SCG_FIRC_CSR_FIRCVLD_MASK))
1016 /* Configure A7 FIRC DIV1 ~ DIV3 */
1017 writel((SCG1_FIRCDIV_DIV3_NUM |
1018 SCG1_FIRCDIV_DIV2_NUM |
1019 SCG1_FIRCDIV_DIV1_NUM), &scg1_regs->fircdiv);
1022 /* SCG1(A7) NICCCR configurations */
1023 /* NIC clock source is DDR clock (396/198MHz) */
1024 #define SCG1_NICCCR_NICCS_NUM ((0x1) << SCG_NICCCR_NICCS_SHIFT)
1026 /* NIC0 clock = DDR Clock / 2 = 396MHz / 2 = 198MHz */
1027 #define SCG1_NICCCR_NIC0_DIV_NUM ((0x1) << SCG_NICCCR_NIC0_DIV_SHIFT)
1028 /* NIC0 clock = DDR Clock / 1 = 198MHz / 1 = 198MHz */
1029 #define SCG1_NICCCR_NIC0_DIV_LF_NUM ((0x0) << SCG_NICCCR_NIC0_DIV_SHIFT)
1030 /* NIC1 clock = NIC0 Clock / 1 = 198MHz / 2 = 198MHz */
1031 #define SCG1_NICCCR_NIC1_DIV_NUM ((0x0) << SCG_NICCCR_NIC1_DIV_SHIFT)
1032 /* NIC1 bus clock = NIC1 Clock / 3 = 198MHz / 3 = 66MHz */
1033 #define SCG1_NICCCR_NIC1_DIVBUS_NUM ((0x2) << SCG_NICCCR_NIC1_DIVBUS_SHIFT)
1034 #define SCG1_NICCCR_CFG_NUM (SCG1_NICCCR_NICCS_NUM | \
1035 SCG1_NICCCR_NIC0_DIV_NUM | \
1036 SCG1_NICCCR_NIC1_DIV_NUM | \
1037 SCG1_NICCCR_NIC1_DIVBUS_NUM)
1039 void scg_a7_nicclk_init(void)
1041 writel(SCG1_NICCCR_CFG_NUM, &scg1_regs->nicccr);
1044 /* SCG1(A7) FIRC DIV configurations */
1045 /* Enable FIRC DIV3 */
1046 #define SCG1_SOSCDIV_DIV3_NUM ((0x1) << SCG_SOSCDIV_DIV3_SHIFT)
1047 /* FIRC DIV2 = 48MHz / 1 = 48MHz */
1048 #define SCG1_SOSCDIV_DIV2_NUM ((0x1) << SCG_SOSCDIV_DIV2_SHIFT)
1049 /* Enable FIRC DIV1 */
1050 #define SCG1_SOSCDIV_DIV1_NUM ((0x1) << SCG_SOSCDIV_DIV1_SHIFT)
1052 void scg_a7_soscdiv_init(void)
1054 /* Wait for FIRC clock ready */
1055 while (!(readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK))
1058 /* Configure A7 FIRC DIV1 ~ DIV3 */
1059 writel((SCG1_SOSCDIV_DIV3_NUM | SCG1_SOSCDIV_DIV2_NUM |
1060 SCG1_SOSCDIV_DIV1_NUM), &scg1_regs->soscdiv);
1063 void scg_a7_sys_clk_sel(enum scg_sys_src clk)
1065 u32 rccr_reg_val = 0;
1067 clk_debug("%s: system clock selected as %s\n", "[SCG]",
1068 clk == SCG_SCS_SYS_OSC ? "SYS_OSC" :
1069 clk == SCG_SCS_SLOW_IRC ? "SLOW_IRC" :
1070 clk == SCG_SCS_FAST_IRC ? "FAST_IRC" :
1071 clk == SCG_SCS_RTC_OSC ? "RTC_OSC" :
1072 clk == SCG_SCS_AUX_PLL ? "AUX_PLL" :
1073 clk == SCG_SCS_SYS_PLL ? "SYS_PLL" :
1074 clk == SCG_SCS_USBPHY_PLL ? "USBPHY_PLL" :
1078 rccr_reg_val = readl(&scg1_regs->rccr);
1079 rccr_reg_val &= ~SCG_CCR_SCS_MASK;
1080 rccr_reg_val |= (clk << SCG_CCR_SCS_SHIFT);
1081 writel(rccr_reg_val, &scg1_regs->rccr);
1084 void scg_a7_info(void)
1086 debug("SCG Version: 0x%x\n", readl(&scg1_regs->verid));
1087 debug("SCG Parameter: 0x%x\n", readl(&scg1_regs->param));
1088 debug("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr));
1089 debug("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr));