1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/pcc.h>
12 #include <asm/arch/sys_proto.h>
14 #define PCC_CLKSRC_TYPES 2
15 #define PCC_CLKSRC_NUM 7
17 static enum scg_clk pcc_clksrc[PCC_CLKSRC_TYPES][PCC_CLKSRC_NUM] = {
26 { SCG_SOSC_DIV2_CLK, /* SOSC BUS clock */
28 SCG_FIRC_DIV2_CLK, /* FIRC BUS clock */
36 static struct pcc_entry pcc_arrays[] = {
37 {PCC2_RBASE, DMA1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
38 {PCC2_RBASE, RGPIO1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
39 {PCC2_RBASE, FLEXBUS0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
40 {PCC2_RBASE, SEMA42_1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
41 {PCC2_RBASE, DMA1_CH_MUX0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
42 {PCC2_RBASE, SNVS_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
43 {PCC2_RBASE, CAAM_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
44 {PCC2_RBASE, LPTPM4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
45 {PCC2_RBASE, LPTPM5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
46 {PCC2_RBASE, LPIT1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
47 {PCC2_RBASE, LPSPI2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
48 {PCC2_RBASE, LPSPI3_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
49 {PCC2_RBASE, LPI2C4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
50 {PCC2_RBASE, LPI2C5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
51 {PCC2_RBASE, LPUART4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
52 {PCC2_RBASE, LPUART5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
53 {PCC2_RBASE, FLEXIO1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
54 {PCC2_RBASE, USBOTG0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
55 {PCC2_RBASE, USBOTG1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
56 {PCC2_RBASE, USBPHY_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
57 {PCC2_RBASE, USB_PL301_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
58 {PCC2_RBASE, USDHC0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
59 {PCC2_RBASE, USDHC1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
60 {PCC2_RBASE, WDG1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
61 {PCC2_RBASE, WDG2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
63 {PCC3_RBASE, LPTPM6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
64 {PCC3_RBASE, LPTPM7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
65 {PCC3_RBASE, LPI2C6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
66 {PCC3_RBASE, LPI2C7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
67 {PCC3_RBASE, LPUART6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
68 {PCC3_RBASE, LPUART7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
69 {PCC3_RBASE, VIU0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
70 {PCC3_RBASE, DSI0_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
71 {PCC3_RBASE, LCDIF0_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
72 {PCC3_RBASE, MMDC0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
73 {PCC3_RBASE, PORTC_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
74 {PCC3_RBASE, PORTD_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
75 {PCC3_RBASE, PORTE_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
76 {PCC3_RBASE, PORTF_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
77 {PCC3_RBASE, GPU3D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
78 {PCC3_RBASE, GPU2D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
81 int pcc_clock_enable(enum pcc_clk clk, bool enable)
85 if (clk >= ARRAY_SIZE(pcc_arrays))
88 reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
92 clk_debug("pcc_clock_enable: clk %d, reg 0x%x, val 0x%x, enable %d\n",
93 clk, reg, val, enable);
95 if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK))
101 val &= ~PCC_CGC_MASK;
105 clk_debug("pcc_clock_enable: val 0x%x\n", val);
110 /* The clock source select needs clock is disabled */
111 int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src)
113 u32 reg, val, i, clksrc_type;
115 if (clk >= ARRAY_SIZE(pcc_arrays))
118 clksrc_type = pcc_arrays[clk].clksrc;
119 if (clksrc_type >= CLKSRC_NO_PCS) {
120 printf("No PCS field for the PCC %d, clksrc type %d\n",
125 for (i = 0; i < PCC_CLKSRC_NUM; i++) {
126 if (pcc_clksrc[clksrc_type][i] == src) {
127 /* Find the clock src, then set it to PCS */
132 if (i == PCC_CLKSRC_NUM) {
133 printf("Not find the parent scg_clk in PCS of PCC %d, invalid scg_clk %d\n", clk, src);
137 reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
141 clk_debug("pcc_clock_sel: clk %d, reg 0x%x, val 0x%x, clksrc_type %d\n",
142 clk, reg, val, clksrc_type);
144 if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
145 (val & PCC_CGC_MASK)) {
146 printf("Not permit to select clock source val = 0x%x\n", val);
150 val &= ~PCC_PCS_MASK;
151 val |= ((i + 1) << PCC_PCS_OFFSET);
155 clk_debug("pcc_clock_sel: val 0x%x\n", val);
160 int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div)
164 if (clk >= ARRAY_SIZE(pcc_arrays) || div > 8 ||
165 (div == 1 && frac != 0))
168 if (pcc_arrays[clk].div >= PCC_NO_DIV) {
169 printf("No DIV/FRAC field for the PCC %d\n", clk);
173 reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
177 if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
178 (val & PCC_CGC_MASK)) {
179 printf("Not permit to set div/frac val = 0x%x\n", val);
184 val |= PCC_FRAC_MASK;
186 val &= ~PCC_FRAC_MASK;
188 val &= ~PCC_PCD_MASK;
189 val |= (div - 1) & PCC_PCD_MASK;
196 bool pcc_clock_is_enable(enum pcc_clk clk)
200 if (clk >= ARRAY_SIZE(pcc_arrays))
203 reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
206 if ((val & PCC_INUSE_MASK) || (val & PCC_CGC_MASK))
212 int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src)
214 u32 reg, val, clksrc_type;
216 if (clk >= ARRAY_SIZE(pcc_arrays))
219 clksrc_type = pcc_arrays[clk].clksrc;
220 if (clksrc_type >= CLKSRC_NO_PCS) {
221 printf("No PCS field for the PCC %d, clksrc type %d\n",
226 reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
230 clk_debug("pcc_clock_get_clksrc: clk %d, reg 0x%x, val 0x%x, type %d\n",
231 clk, reg, val, clksrc_type);
233 if (!(val & PCC_PR_MASK)) {
234 printf("This pcc slot is not present = 0x%x\n", val);
239 val = (val >> PCC_PCS_OFFSET);
242 printf("Clock source is off\n");
246 *src = pcc_clksrc[clksrc_type][val - 1];
248 clk_debug("pcc_clock_get_clksrc: parent scg clk %d\n", *src);
253 u32 pcc_clock_get_rate(enum pcc_clk clk)
255 u32 reg, val, rate, frac, div;
259 ret = pcc_clock_get_clksrc(clk, &parent);
263 rate = scg_clk_get_rate(parent);
265 clk_debug("pcc_clock_get_rate: parent rate %u\n", rate);
267 if (pcc_arrays[clk].div == PCC_HAS_DIV) {
268 reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
271 frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET;
272 div = (val & PCC_PCD_MASK) >> PCC_PCD_OFFSET;
275 * Theoretically don't have overflow in the calc,
276 * the rate won't exceed 2G
278 rate = rate * (frac + 1) / (div + 1);
281 clk_debug("pcc_clock_get_rate: rate %u\n", rate);