1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/mach-imx/dma.h>
12 #include <asm/mach-imx/hab.h>
13 #include <asm/mach-imx/rdc-sema.h>
14 #include <asm/arch/imx-rdc.h>
15 #include <asm/arch/crm_regs.h>
18 #include <imx_thermal.h>
20 #include <asm/setup.h>
22 #define IOMUXC_GPR1 0x4
23 #define BM_IOMUXC_GPR1_IRQ 0x1000
25 #define GPC_LPCR_A7_BSC 0x0
26 #define GPC_LPCR_M4 0x8
27 #define GPC_SLPCR 0x14
28 #define GPC_PGC_ACK_SEL_A7 0x24
29 #define GPC_IMR1_CORE0 0x30
30 #define GPC_IMR1_CORE1 0x40
31 #define GPC_IMR1_M4 0x50
32 #define GPC_PGC_CPU_MAPPING 0xec
33 #define GPC_PGC_C0_PUPSCR 0x804
34 #define GPC_PGC_SCU_TIMING 0x890
35 #define GPC_PGC_C1_PUPSCR 0x844
37 #define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000
38 #define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
39 #define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000
40 #define BM_SLPCR_EN_DSM 0x80000000
41 #define BM_SLPCR_RBC_EN 0x40000000
42 #define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
43 #define BM_SLPCR_VSTBY 0x4
44 #define BM_SLPCR_SBYOS 0x2
45 #define BM_SLPCR_BYPASS_PMIC_READY 0x1
46 #define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000
48 #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000
49 #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000
51 #define BM_GPC_PGC_CORE_PUPSCR 0x7fff80
53 #if defined(CONFIG_IMX_THERMAL)
54 static const struct imx_thermal_plat imx7_thermal_plat = {
55 .regs = (void *)ANATOP_BASE_ADDR,
60 U_BOOT_DEVICE(imx7_thermal) = {
61 .name = "imx_thermal",
62 .platdata = &imx7_thermal_plat,
66 #if CONFIG_IS_ENABLED(IMX_RDC)
68 * In current design, if any peripheral was assigned to both A7 and M4,
69 * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
70 * low power mode. So M4 sleep will cause some peripherals fail to work
71 * at A7 core side. At default, all resources are in domain 0 - 3.
73 * There are 26 peripherals impacted by this IC issue:
76 * UART1/UART2/UART3/UART4/UART5/UART6/UART7
78 * WDOG1/WDOG2/WDOG3/WDOG4
82 * Software Workaround:
83 * Here we setup some resources to domain 0 where M4 codes will move
84 * the M4 out of this domain. Then M4 is not able to access them any longer.
85 * This is a workaround for ic issue. So the peripherals are not shared
86 * by them. This way requires the uboot implemented the RDC driver and
87 * set the 26 IPs above to domain 0 only. M4 code will assign resource
88 * to its own domain, if it want to use the resource.
90 static rdc_peri_cfg_t const resources[] = {
91 (RDC_PER_SIM1 | RDC_DOMAIN(0)),
92 (RDC_PER_SIM2 | RDC_DOMAIN(0)),
93 (RDC_PER_UART1 | RDC_DOMAIN(0)),
94 (RDC_PER_UART2 | RDC_DOMAIN(0)),
95 (RDC_PER_UART3 | RDC_DOMAIN(0)),
96 (RDC_PER_UART4 | RDC_DOMAIN(0)),
97 (RDC_PER_UART5 | RDC_DOMAIN(0)),
98 (RDC_PER_UART6 | RDC_DOMAIN(0)),
99 (RDC_PER_UART7 | RDC_DOMAIN(0)),
100 (RDC_PER_SAI1 | RDC_DOMAIN(0)),
101 (RDC_PER_SAI2 | RDC_DOMAIN(0)),
102 (RDC_PER_SAI3 | RDC_DOMAIN(0)),
103 (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
104 (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
105 (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
106 (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
107 (RDC_PER_GPT1 | RDC_DOMAIN(0)),
108 (RDC_PER_GPT2 | RDC_DOMAIN(0)),
109 (RDC_PER_GPT3 | RDC_DOMAIN(0)),
110 (RDC_PER_GPT4 | RDC_DOMAIN(0)),
111 (RDC_PER_PWM1 | RDC_DOMAIN(0)),
112 (RDC_PER_PWM2 | RDC_DOMAIN(0)),
113 (RDC_PER_PWM3 | RDC_DOMAIN(0)),
114 (RDC_PER_PWM4 | RDC_DOMAIN(0)),
115 (RDC_PER_ENET1 | RDC_DOMAIN(0)),
116 (RDC_PER_ENET2 | RDC_DOMAIN(0)),
119 static void isolate_resource(void)
121 imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
125 #if defined(CONFIG_IMX_HAB)
126 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
132 static bool is_mx7d(void)
134 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
135 struct fuse_bank *bank = &ocotp->bank[1];
136 struct fuse_bank1_regs *fuse =
137 (struct fuse_bank1_regs *)bank->fuse_regs;
140 val = readl(&fuse->tester4);
147 u32 get_cpu_rev(void)
149 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
151 u32 reg = readl(&ccm_anatop->digprog);
152 u32 type = (reg >> 16) & 0xff;
158 return (type << 12) | reg;
161 #ifdef CONFIG_REVISION_TAG
162 u32 __weak get_board_rev(void)
164 return get_cpu_rev();
168 static void imx_enet_mdio_fixup(void)
170 struct iomuxc_gpr_base_regs *gpr_regs =
171 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
174 * The management data input/output (MDIO) requires open-drain,
175 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
176 * this feature. So to TO1.1, need to enable open drain by setting
180 if (soc_rev() >= CHIP_REV_1_1) {
181 setbits_le32(&gpr_regs->gpr[0],
182 IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
186 static void init_cpu_basic(void)
188 imx_enet_mdio_fixup();
190 #ifdef CONFIG_APBH_DMA
196 #ifdef CONFIG_IMX_BOOTAUX
198 * Table of mappings of physical mem regions in both
199 * Cortex-A7 and Cortex-M4 address spaces.
201 * For additional details check sections 2.1.2 and 2.1.3 in
202 * i.MX7Dual Applications Processor Reference Manual
205 const struct rproc_att hostmap[] = {
206 /* aux core , host core, size */
207 { 0x00000000, 0x00180000, 0x8000 }, /* OCRAM_S */
208 { 0x00180000, 0x00180000, 0x8000 }, /* OCRAM_S */
209 { 0x20180000, 0x00180000, 0x8000 }, /* OCRAM_S */
210 { 0x1fff8000, 0x007f8000, 0x8000 }, /* TCML */
211 { 0x20000000, 0x00800000, 0x8000 }, /* TCMU */
212 { 0x00900000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
213 { 0x20200000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
214 { 0x00920000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
215 { 0x20220000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
216 { 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
217 { 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
218 { 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */
219 { 0x80000000, 0x80000000, 0xe0000000 }, /* DDRC */
224 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
225 /* enable all periherial can be accessed in nosec mode */
226 static void init_csu(void)
230 for (i = 0; i < CSU_NUM_REGS; i++)
231 writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
234 static void imx_gpcv2_init(void)
239 * Force IOMUXC irq pending, so that the interrupt to GPC can be
240 * used to deassert dsm_request signal when the signal gets
241 * asserted unexpectedly.
243 val = readl(IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
244 val |= BM_IOMUXC_GPR1_IRQ;
245 writel(val, IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
247 /* Initially mask all interrupts */
248 for (i = 0; i < 4; i++) {
249 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
250 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4);
251 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_M4 + i * 4);
255 writel((0x59 << 10) | 0x5B | (0x2 << 20),
256 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING);
258 /* only external IRQs to wake up LPM and core 0/1 */
259 val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
260 val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP;
261 writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
263 /* set C0 power up timming per design requirement */
264 val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
265 val &= ~BM_GPC_PGC_CORE_PUPSCR;
267 writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
269 /* set C1 power up timming per design requirement */
270 val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
271 val &= ~BM_GPC_PGC_CORE_PUPSCR;
273 writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
275 /* dummy ack for time slot by default */
276 writel(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK |
277 BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
278 GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
280 /* mask M4 DSM trigger */
281 writel(readl(GPC_IPS_BASE_ADDR + GPC_LPCR_M4) |
282 BM_LPCR_M4_MASK_DSM_TRIGGER,
283 GPC_IPS_BASE_ADDR + GPC_LPCR_M4);
285 /* set mega/fast mix in A7 domain */
286 writel(0x1, GPC_IPS_BASE_ADDR + GPC_PGC_CPU_MAPPING);
288 /* DSM related settings */
289 val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
290 val &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
291 BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY |
292 BM_SLPCR_REG_BYPASS_COUNT);
293 val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE;
294 writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
297 * disabling RBC need to delay at least 2 cycles of CKIL(32K)
298 * due to hardware design requirement, which is
299 * ~61us, here we use 65us for safe
304 int arch_cpu_init(void)
309 /* Disable PDE bit of WMCR register */
310 imx_wdog_disable_powerdown();
314 #if CONFIG_IS_ENABLED(IMX_RDC)
325 int arch_cpu_init(void)
333 #ifdef CONFIG_ARCH_MISC_INIT
334 int arch_misc_init(void)
336 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
338 env_set("soc", "imx7d");
340 env_set("soc", "imx7s");
343 #ifdef CONFIG_FSL_CAAM
351 #ifdef CONFIG_SERIAL_TAG
354 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
355 * OCOTP_TESTER describes a unique ID based on silicon wafer
356 * and die X/Y position
358 * OCOTOP_TESTER offset 0x410
360 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
362 * OCOTP_TESTER1 offset 0x420
364 * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
366 * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
368 * The wafer number of the wafer on which the device was fabricated/SJC
369 * CHALLENGE/ Unique ID
371 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
373 void get_board_serial(struct tag_serialnr *serialnr)
375 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
376 struct fuse_bank *bank = &ocotp->bank[0];
377 struct fuse_bank0_regs *fuse =
378 (struct fuse_bank0_regs *)bank->fuse_regs;
380 serialnr->low = fuse->tester0;
381 serialnr->high = fuse->tester1;
385 void set_wdog_reset(struct wdog_regs *wdog)
387 u32 reg = readw(&wdog->wcr);
389 * Output WDOG_B signal to reset external pmic or POR_B decided by
390 * the board desgin. Without external reset, the peripherals/DDR/
391 * PMIC are not reset, that may cause system working abnormal.
393 reg = readw(&wdog->wcr);
396 * WDZST bit is write-once only bit. Align this bit in kernel,
397 * otherwise kernel code will have no chance to set this bit.
400 writew(reg, &wdog->wcr);
405 /* clock configuration. */
411 void reset_misc(void)
413 #ifndef CONFIG_SPL_BUILD
414 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)