1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/mach-imx/dma.h>
12 #include <asm/mach-imx/hab.h>
13 #include <asm/mach-imx/rdc-sema.h>
14 #include <asm/arch/imx-rdc.h>
15 #include <asm/arch/crm_regs.h>
17 #include <imx_thermal.h>
19 #include <asm/setup.h>
21 #define IOMUXC_GPR1 0x4
22 #define BM_IOMUXC_GPR1_IRQ 0x1000
24 #define GPC_LPCR_A7_BSC 0x0
25 #define GPC_LPCR_M4 0x8
26 #define GPC_SLPCR 0x14
27 #define GPC_PGC_ACK_SEL_A7 0x24
28 #define GPC_IMR1_CORE0 0x30
29 #define GPC_IMR1_CORE1 0x40
30 #define GPC_IMR1_M4 0x50
31 #define GPC_PGC_CPU_MAPPING 0xec
32 #define GPC_PGC_C0_PUPSCR 0x804
33 #define GPC_PGC_SCU_TIMING 0x890
34 #define GPC_PGC_C1_PUPSCR 0x844
36 #define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000
37 #define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
38 #define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000
39 #define BM_SLPCR_EN_DSM 0x80000000
40 #define BM_SLPCR_RBC_EN 0x40000000
41 #define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
42 #define BM_SLPCR_VSTBY 0x4
43 #define BM_SLPCR_SBYOS 0x2
44 #define BM_SLPCR_BYPASS_PMIC_READY 0x1
45 #define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000
47 #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000
48 #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000
50 #define BM_GPC_PGC_CORE_PUPSCR 0x7fff80
52 #if defined(CONFIG_IMX_THERMAL)
53 static const struct imx_thermal_plat imx7_thermal_plat = {
54 .regs = (void *)ANATOP_BASE_ADDR,
59 U_BOOT_DEVICE(imx7_thermal) = {
60 .name = "imx_thermal",
61 .platdata = &imx7_thermal_plat,
65 #if CONFIG_IS_ENABLED(IMX_RDC)
67 * In current design, if any peripheral was assigned to both A7 and M4,
68 * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
69 * low power mode. So M4 sleep will cause some peripherals fail to work
70 * at A7 core side. At default, all resources are in domain 0 - 3.
72 * There are 26 peripherals impacted by this IC issue:
75 * UART1/UART2/UART3/UART4/UART5/UART6/UART7
77 * WDOG1/WDOG2/WDOG3/WDOG4
81 * Software Workaround:
82 * Here we setup some resources to domain 0 where M4 codes will move
83 * the M4 out of this domain. Then M4 is not able to access them any longer.
84 * This is a workaround for ic issue. So the peripherals are not shared
85 * by them. This way requires the uboot implemented the RDC driver and
86 * set the 26 IPs above to domain 0 only. M4 code will assign resource
87 * to its own domain, if it want to use the resource.
89 static rdc_peri_cfg_t const resources[] = {
90 (RDC_PER_SIM1 | RDC_DOMAIN(0)),
91 (RDC_PER_SIM2 | RDC_DOMAIN(0)),
92 (RDC_PER_UART1 | RDC_DOMAIN(0)),
93 (RDC_PER_UART2 | RDC_DOMAIN(0)),
94 (RDC_PER_UART3 | RDC_DOMAIN(0)),
95 (RDC_PER_UART4 | RDC_DOMAIN(0)),
96 (RDC_PER_UART5 | RDC_DOMAIN(0)),
97 (RDC_PER_UART6 | RDC_DOMAIN(0)),
98 (RDC_PER_UART7 | RDC_DOMAIN(0)),
99 (RDC_PER_SAI1 | RDC_DOMAIN(0)),
100 (RDC_PER_SAI2 | RDC_DOMAIN(0)),
101 (RDC_PER_SAI3 | RDC_DOMAIN(0)),
102 (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
103 (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
104 (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
105 (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
106 (RDC_PER_GPT1 | RDC_DOMAIN(0)),
107 (RDC_PER_GPT2 | RDC_DOMAIN(0)),
108 (RDC_PER_GPT3 | RDC_DOMAIN(0)),
109 (RDC_PER_GPT4 | RDC_DOMAIN(0)),
110 (RDC_PER_PWM1 | RDC_DOMAIN(0)),
111 (RDC_PER_PWM2 | RDC_DOMAIN(0)),
112 (RDC_PER_PWM3 | RDC_DOMAIN(0)),
113 (RDC_PER_PWM4 | RDC_DOMAIN(0)),
114 (RDC_PER_ENET1 | RDC_DOMAIN(0)),
115 (RDC_PER_ENET2 | RDC_DOMAIN(0)),
118 static void isolate_resource(void)
120 imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
124 #if defined(CONFIG_SECURE_BOOT)
125 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
131 static bool is_mx7d(void)
133 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
134 struct fuse_bank *bank = &ocotp->bank[1];
135 struct fuse_bank1_regs *fuse =
136 (struct fuse_bank1_regs *)bank->fuse_regs;
139 val = readl(&fuse->tester4);
146 u32 get_cpu_rev(void)
148 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
150 u32 reg = readl(&ccm_anatop->digprog);
151 u32 type = (reg >> 16) & 0xff;
157 return (type << 12) | reg;
160 #ifdef CONFIG_REVISION_TAG
161 u32 __weak get_board_rev(void)
163 return get_cpu_rev();
167 static void imx_enet_mdio_fixup(void)
169 struct iomuxc_gpr_base_regs *gpr_regs =
170 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
173 * The management data input/output (MDIO) requires open-drain,
174 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
175 * this feature. So to TO1.1, need to enable open drain by setting
179 if (soc_rev() >= CHIP_REV_1_1) {
180 setbits_le32(&gpr_regs->gpr[0],
181 IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
185 static void init_cpu_basic(void)
187 imx_enet_mdio_fixup();
189 #ifdef CONFIG_APBH_DMA
195 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
196 /* enable all periherial can be accessed in nosec mode */
197 static void init_csu(void)
201 for (i = 0; i < CSU_NUM_REGS; i++)
202 writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
205 static void imx_gpcv2_init(void)
210 * Force IOMUXC irq pending, so that the interrupt to GPC can be
211 * used to deassert dsm_request signal when the signal gets
212 * asserted unexpectedly.
214 val = readl(IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
215 val |= BM_IOMUXC_GPR1_IRQ;
216 writel(val, IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
218 /* Initially mask all interrupts */
219 for (i = 0; i < 4; i++) {
220 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
221 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4);
222 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_M4 + i * 4);
226 writel((0x59 << 10) | 0x5B | (0x2 << 20),
227 GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING);
229 /* only external IRQs to wake up LPM and core 0/1 */
230 val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
231 val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP;
232 writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
234 /* set C0 power up timming per design requirement */
235 val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
236 val &= ~BM_GPC_PGC_CORE_PUPSCR;
238 writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
240 /* set C1 power up timming per design requirement */
241 val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
242 val &= ~BM_GPC_PGC_CORE_PUPSCR;
244 writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
246 /* dummy ack for time slot by default */
247 writel(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK |
248 BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
249 GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
251 /* mask M4 DSM trigger */
252 writel(readl(GPC_IPS_BASE_ADDR + GPC_LPCR_M4) |
253 BM_LPCR_M4_MASK_DSM_TRIGGER,
254 GPC_IPS_BASE_ADDR + GPC_LPCR_M4);
256 /* set mega/fast mix in A7 domain */
257 writel(0x1, GPC_IPS_BASE_ADDR + GPC_PGC_CPU_MAPPING);
259 /* DSM related settings */
260 val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
261 val &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
262 BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY |
263 BM_SLPCR_REG_BYPASS_COUNT);
264 val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE;
265 writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
268 * disabling RBC need to delay at least 2 cycles of CKIL(32K)
269 * due to hardware design requirement, which is
270 * ~61us, here we use 65us for safe
275 int arch_cpu_init(void)
280 /* Disable PDE bit of WMCR register */
281 imx_wdog_disable_powerdown();
285 #if CONFIG_IS_ENABLED(IMX_RDC)
296 int arch_cpu_init(void)
304 #ifdef CONFIG_ARCH_MISC_INIT
305 int arch_misc_init(void)
307 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
309 env_set("soc", "imx7d");
311 env_set("soc", "imx7s");
314 #ifdef CONFIG_FSL_CAAM
322 #ifdef CONFIG_SERIAL_TAG
325 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
326 * OCOTP_TESTER describes a unique ID based on silicon wafer
327 * and die X/Y position
329 * OCOTOP_TESTER offset 0x410
331 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
333 * OCOTP_TESTER1 offset 0x420
335 * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
337 * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
339 * The wafer number of the wafer on which the device was fabricated/SJC
340 * CHALLENGE/ Unique ID
342 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
344 void get_board_serial(struct tag_serialnr *serialnr)
346 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
347 struct fuse_bank *bank = &ocotp->bank[0];
348 struct fuse_bank0_regs *fuse =
349 (struct fuse_bank0_regs *)bank->fuse_regs;
351 serialnr->low = fuse->tester0;
352 serialnr->high = fuse->tester1;
356 void set_wdog_reset(struct wdog_regs *wdog)
358 u32 reg = readw(&wdog->wcr);
360 * Output WDOG_B signal to reset external pmic or POR_B decided by
361 * the board desgin. Without external reset, the peripherals/DDR/
362 * PMIC are not reset, that may cause system working abnormal.
364 reg = readw(&wdog->wcr);
367 * WDZST bit is write-once only bit. Align this bit in kernel,
368 * otherwise kernel code will have no chance to set this bit.
371 writew(reg, &wdog->wcr);
376 /* clock configuration. */
382 void reset_misc(void)
384 #ifndef CONFIG_SPL_BUILD
385 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)