1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
6 * Peng Fan <Peng.Fan@freescale.com>
12 #include <linux/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/crm_regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
18 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
20 struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
22 #ifdef CONFIG_FSL_ESDHC_IMX
23 DECLARE_GLOBAL_DATA_PTR;
28 #ifdef CONFIG_FSL_ESDHC_IMX
29 #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
30 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
31 #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
32 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
34 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
42 return get_root_clk(AHB_CLK_ROOT);
45 static u32 get_ipg_clk(void)
48 * The AHB and IPG are fixed at 2:1 ratio, and synchronized to
51 return get_ahb_clk() / 2;
54 u32 imx_get_uartclk(void)
56 return get_root_clk(UART_CLK_ROOT);
59 u32 imx_get_fecclk(void)
61 return get_root_clk(ENET_AXI_CLK_ROOT);
64 #ifdef CONFIG_MXC_OCOTP
65 void enable_ocotp_clk(unsigned char enable)
67 clock_enable(CCGR_OCOTP, enable);
70 void enable_thermal_clk(void)
76 void enable_usboh3_clk(unsigned char enable)
81 /* disable the clock gate first */
82 clock_enable(CCGR_USB_HSIC, 0);
85 target = CLK_ROOT_ON |
86 USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
87 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
88 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
89 clock_set_target_val(USB_HSIC_CLK_ROOT, target);
91 /* enable the clock gate */
92 clock_enable(CCGR_USB_CTRL, 1);
93 clock_enable(CCGR_USB_HSIC, 1);
94 clock_enable(CCGR_USB_PHY1, 1);
95 clock_enable(CCGR_USB_PHY2, 1);
97 clock_enable(CCGR_USB_CTRL, 0);
98 clock_enable(CCGR_USB_HSIC, 0);
99 clock_enable(CCGR_USB_PHY1, 0);
100 clock_enable(CCGR_USB_PHY2, 0);
104 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
110 * Alought there are four choices for the bypass src,
111 * we choose OSC_24M which is the default set in ROM.
115 reg = readl(&ccm_anatop->pll_arm);
117 if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
120 if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
123 div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
124 CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT;
126 return (infreq * div_sel) / 2;
129 reg = readl(&ccm_anatop->pll_480);
131 if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK)
134 if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK)
137 if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >>
138 CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0)
144 reg = readl(&ccm_anatop->pll_enet);
146 if (reg & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
149 if (reg & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
155 reg = readl(&ccm_anatop->pll_ddr);
157 if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK)
160 num = ccm_anatop->pll_ddr_num;
161 denom = ccm_anatop->pll_ddr_denom;
163 if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK)
166 div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >>
167 CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT;
169 return infreq * (div_sel + num / denom);
175 printf("Unsupported pll clocks %d\n", pll);
182 static u32 mxc_get_pll_sys_derive(int derive)
188 reg = readl(&ccm_anatop->pll_480);
189 freq = decode_pll(PLL_SYS, MXC_HCLK);
192 case PLL_SYS_MAIN_480M_CLK:
193 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK)
197 case PLL_SYS_MAIN_240M_CLK:
198 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK)
202 case PLL_SYS_MAIN_120M_CLK:
203 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK)
207 case PLL_SYS_PFD0_392M_CLK:
208 reg = readl(&ccm_anatop->pfd_480a);
209 if (reg & CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK)
211 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
212 CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
214 case PLL_SYS_PFD0_196M_CLK:
215 if (reg & CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK)
217 reg = readl(&ccm_anatop->pfd_480a);
218 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
219 CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
222 case PLL_SYS_PFD1_332M_CLK:
223 reg = readl(&ccm_anatop->pfd_480a);
224 if (reg & CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK)
226 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
227 CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
229 case PLL_SYS_PFD1_166M_CLK:
230 if (reg & CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK)
232 reg = readl(&ccm_anatop->pfd_480a);
233 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
234 CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
237 case PLL_SYS_PFD2_270M_CLK:
238 reg = readl(&ccm_anatop->pfd_480a);
239 if (reg & CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK)
241 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
242 CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
244 case PLL_SYS_PFD2_135M_CLK:
245 if (reg & CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK)
247 reg = readl(&ccm_anatop->pfd_480a);
248 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
249 CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
252 case PLL_SYS_PFD3_CLK:
253 reg = readl(&ccm_anatop->pfd_480a);
254 if (reg & CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK)
256 frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >>
257 CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT;
259 case PLL_SYS_PFD4_CLK:
260 reg = readl(&ccm_anatop->pfd_480b);
261 if (reg & CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK)
263 frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >>
264 CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT;
266 case PLL_SYS_PFD5_CLK:
267 reg = readl(&ccm_anatop->pfd_480b);
268 if (reg & CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK)
270 frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >>
271 CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT;
273 case PLL_SYS_PFD6_CLK:
274 reg = readl(&ccm_anatop->pfd_480b);
275 if (reg & CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK)
277 frac = (reg & CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) >>
278 CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT;
280 case PLL_SYS_PFD7_CLK:
281 reg = readl(&ccm_anatop->pfd_480b);
282 if (reg & CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK)
284 frac = (reg & CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) >>
285 CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT;
288 printf("Error derived pll_sys clock %d\n", derive);
292 return ((freq / frac) * 18) / div;
295 static u32 mxc_get_pll_enet_derive(int derive)
299 freq = decode_pll(PLL_ENET, MXC_HCLK);
300 reg = readl(&ccm_anatop->pll_enet);
303 case PLL_ENET_MAIN_500M_CLK:
304 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK)
307 case PLL_ENET_MAIN_250M_CLK:
308 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK)
311 case PLL_ENET_MAIN_125M_CLK:
312 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK)
315 case PLL_ENET_MAIN_100M_CLK:
316 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK)
319 case PLL_ENET_MAIN_50M_CLK:
320 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK)
323 case PLL_ENET_MAIN_40M_CLK:
324 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK)
327 case PLL_ENET_MAIN_25M_CLK:
328 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK)
332 printf("Error derived pll_enet clock %d\n", derive);
339 static u32 mxc_get_pll_ddr_derive(int derive)
343 freq = decode_pll(PLL_DDR, MXC_HCLK);
344 reg = readl(&ccm_anatop->pll_ddr);
347 case PLL_DRAM_MAIN_1066M_CLK:
349 case PLL_DRAM_MAIN_533M_CLK:
350 if (reg & CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK)
354 printf("Error derived pll_ddr clock %d\n", derive);
361 static u32 mxc_get_pll_derive(enum pll_clocks pll, int derive)
365 return mxc_get_pll_sys_derive(derive);
367 return mxc_get_pll_enet_derive(derive);
369 return mxc_get_pll_ddr_derive(derive);
371 printf("Error pll.\n");
376 static u32 get_root_src_clk(enum clk_root_src root_src)
381 case PLL_ARM_MAIN_800M_CLK:
382 return decode_pll(PLL_CORE, MXC_HCLK);
384 case PLL_SYS_MAIN_480M_CLK:
385 case PLL_SYS_MAIN_240M_CLK:
386 case PLL_SYS_MAIN_120M_CLK:
387 case PLL_SYS_PFD0_392M_CLK:
388 case PLL_SYS_PFD0_196M_CLK:
389 case PLL_SYS_PFD1_332M_CLK:
390 case PLL_SYS_PFD1_166M_CLK:
391 case PLL_SYS_PFD2_270M_CLK:
392 case PLL_SYS_PFD2_135M_CLK:
393 case PLL_SYS_PFD3_CLK:
394 case PLL_SYS_PFD4_CLK:
395 case PLL_SYS_PFD5_CLK:
396 case PLL_SYS_PFD6_CLK:
397 case PLL_SYS_PFD7_CLK:
398 return mxc_get_pll_derive(PLL_SYS, root_src);
400 case PLL_ENET_MAIN_500M_CLK:
401 case PLL_ENET_MAIN_250M_CLK:
402 case PLL_ENET_MAIN_125M_CLK:
403 case PLL_ENET_MAIN_100M_CLK:
404 case PLL_ENET_MAIN_50M_CLK:
405 case PLL_ENET_MAIN_40M_CLK:
406 case PLL_ENET_MAIN_25M_CLK:
407 return mxc_get_pll_derive(PLL_ENET, root_src);
409 case PLL_DRAM_MAIN_1066M_CLK:
410 case PLL_DRAM_MAIN_533M_CLK:
411 return mxc_get_pll_derive(PLL_DDR, root_src);
413 case PLL_AUDIO_MAIN_CLK:
414 return decode_pll(PLL_AUDIO, MXC_HCLK);
415 case PLL_VIDEO_MAIN_CLK:
416 return decode_pll(PLL_VIDEO, MXC_HCLK);
418 case PLL_USB_MAIN_480M_CLK:
419 return decode_pll(PLL_USB, MXC_HCLK);
430 printf("No EXT CLK supported??\n");
437 u32 get_root_clk(enum clk_root_index clock_id)
439 enum clk_root_src root_src;
440 u32 post_podf, pre_podf, auto_podf, root_src_clk;
443 if (clock_root_enabled(clock_id) <= 0)
446 if (clock_get_prediv(clock_id, &pre_podf) < 0)
449 if (clock_get_postdiv(clock_id, &post_podf) < 0)
452 if (clock_get_autopostdiv(clock_id, &auto_podf, &auto_en) < 0)
458 if (clock_get_src(clock_id, &root_src) < 0)
461 root_src_clk = get_root_src_clk(root_src);
464 * bypass clk is ignored.
467 return root_src_clk / (post_podf + 1) / (pre_podf + 1) /
471 static u32 get_ddrc_clk(void)
474 enum root_post_div post_div;
476 reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root);
477 if (reg & CLK_ROOT_MUX_MASK)
478 /* DRAM_ALT_CLK_ROOT */
479 freq = get_root_clk(DRAM_ALT_CLK_ROOT);
481 /* PLL_DRAM_MAIN_1066M_CLK */
482 freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK);
484 post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK;
486 return freq / (post_div + 1) / 2;
489 unsigned int mxc_get_clock(enum mxc_clock clk)
493 return get_root_clk(ARM_A7_CLK_ROOT);
495 return get_root_clk(MAIN_AXI_CLK_ROOT);
497 return get_root_clk(AHB_CLK_ROOT);
499 return get_ipg_clk();
501 return get_root_clk(I2C1_CLK_ROOT);
503 return get_root_clk(UART1_CLK_ROOT);
505 return get_root_clk(ECSPI1_CLK_ROOT);
507 return get_ddrc_clk();
509 return get_root_clk(USDHC1_CLK_ROOT);
511 return get_root_clk(USDHC2_CLK_ROOT);
513 return get_root_clk(USDHC3_CLK_ROOT);
515 printf("Unsupported mxc_clock %d\n", clk);
522 #ifdef CONFIG_SYS_I2C_MXC
523 /* i2c_num can be 0 - 3 */
524 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
532 clock_enable(CCGR_I2C1 + i2c_num, 0);
534 /* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */
536 target = CLK_ROOT_ON |
537 I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
538 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
539 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
540 clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target);
542 clock_enable(CCGR_I2C1 + i2c_num, 1);
544 clock_enable(CCGR_I2C1 + i2c_num, 0);
551 static void init_clk_esdhc(void)
555 /* disable the clock gate first */
556 clock_enable(CCGR_USDHC1, 0);
557 clock_enable(CCGR_USDHC2, 0);
558 clock_enable(CCGR_USDHC3, 0);
561 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
562 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
563 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
564 clock_set_target_val(USDHC1_CLK_ROOT, target);
566 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
567 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
568 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
569 clock_set_target_val(USDHC2_CLK_ROOT, target);
571 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
572 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
573 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
574 clock_set_target_val(USDHC3_CLK_ROOT, target);
576 /* enable the clock gate */
577 clock_enable(CCGR_USDHC1, 1);
578 clock_enable(CCGR_USDHC2, 1);
579 clock_enable(CCGR_USDHC3, 1);
582 static void init_clk_uart(void)
586 /* disable the clock gate first */
587 clock_enable(CCGR_UART1, 0);
588 clock_enable(CCGR_UART2, 0);
589 clock_enable(CCGR_UART3, 0);
590 clock_enable(CCGR_UART4, 0);
591 clock_enable(CCGR_UART5, 0);
592 clock_enable(CCGR_UART6, 0);
593 clock_enable(CCGR_UART7, 0);
596 target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |
597 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
598 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
599 clock_set_target_val(UART1_CLK_ROOT, target);
601 target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |
602 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
603 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
604 clock_set_target_val(UART2_CLK_ROOT, target);
606 target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |
607 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
608 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
609 clock_set_target_val(UART3_CLK_ROOT, target);
611 target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |
612 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
613 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
614 clock_set_target_val(UART4_CLK_ROOT, target);
616 target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK |
617 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
618 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
619 clock_set_target_val(UART5_CLK_ROOT, target);
621 target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK |
622 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
623 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
624 clock_set_target_val(UART6_CLK_ROOT, target);
626 target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK |
627 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
628 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
629 clock_set_target_val(UART7_CLK_ROOT, target);
631 /* enable the clock gate */
632 clock_enable(CCGR_UART1, 1);
633 clock_enable(CCGR_UART2, 1);
634 clock_enable(CCGR_UART3, 1);
635 clock_enable(CCGR_UART4, 1);
636 clock_enable(CCGR_UART5, 1);
637 clock_enable(CCGR_UART6, 1);
638 clock_enable(CCGR_UART7, 1);
641 static void init_clk_weim(void)
645 /* disable the clock gate first */
646 clock_enable(CCGR_WEIM, 0);
649 target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
650 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
651 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
652 clock_set_target_val(EIM_CLK_ROOT, target);
654 /* enable the clock gate */
655 clock_enable(CCGR_WEIM, 1);
658 static void init_clk_ecspi(void)
662 /* disable the clock gate first */
663 clock_enable(CCGR_ECSPI1, 0);
664 clock_enable(CCGR_ECSPI2, 0);
665 clock_enable(CCGR_ECSPI3, 0);
666 clock_enable(CCGR_ECSPI4, 0);
669 target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
670 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
671 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
672 clock_set_target_val(ECSPI1_CLK_ROOT, target);
674 target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
675 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
676 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
677 clock_set_target_val(ECSPI2_CLK_ROOT, target);
679 target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
680 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
681 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
682 clock_set_target_val(ECSPI3_CLK_ROOT, target);
684 target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
685 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
686 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
687 clock_set_target_val(ECSPI4_CLK_ROOT, target);
689 /* enable the clock gate */
690 clock_enable(CCGR_ECSPI1, 1);
691 clock_enable(CCGR_ECSPI2, 1);
692 clock_enable(CCGR_ECSPI3, 1);
693 clock_enable(CCGR_ECSPI4, 1);
696 static void init_clk_wdog(void)
700 /* disable the clock gate first */
701 clock_enable(CCGR_WDOG1, 0);
702 clock_enable(CCGR_WDOG2, 0);
703 clock_enable(CCGR_WDOG3, 0);
704 clock_enable(CCGR_WDOG4, 0);
707 target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK |
708 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
709 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
710 clock_set_target_val(WDOG_CLK_ROOT, target);
712 /* enable the clock gate */
713 clock_enable(CCGR_WDOG1, 1);
714 clock_enable(CCGR_WDOG2, 1);
715 clock_enable(CCGR_WDOG3, 1);
716 clock_enable(CCGR_WDOG4, 1);
719 #ifdef CONFIG_MXC_EPDC
720 static void init_clk_epdc(void)
724 /* disable the clock gate first */
725 clock_enable(CCGR_EPDC, 0);
728 target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
729 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
730 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12);
731 clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target);
733 /* enable the clock gate */
734 clock_enable(CCGR_EPDC, 1);
738 static int enable_pll_enet(void)
741 s32 timeout = 100000;
743 reg = readl(&ccm_anatop->pll_enet);
744 /* If pll_enet powered up, no need to set it again */
745 if (reg & ANADIG_PLL_ENET_PWDN_MASK) {
746 reg &= ~ANADIG_PLL_ENET_PWDN_MASK;
747 writel(reg, &ccm_anatop->pll_enet);
750 if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK)
755 /* If timeout, we set pwdn for pll_enet. */
756 reg |= ANADIG_PLL_ENET_PWDN_MASK;
762 writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr);
764 writel((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK
765 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK
766 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK
767 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK
768 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK
769 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK
770 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK),
771 &ccm_anatop->pll_enet_set);
775 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
781 debug("pll5 div = %d, num = %d, denom = %d\n",
782 pll_div, pll_num, pll_denom);
784 /* Power up PLL5 video and disable its output */
785 writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK |
786 CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK |
787 CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK |
788 CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK |
789 CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK |
790 CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK,
791 &ccm_anatop->pll_video_clr);
793 /* Set div, num and denom */
796 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
797 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x1) |
798 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
799 &ccm_anatop->pll_video_set);
802 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
803 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
804 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
805 &ccm_anatop->pll_video_set);
808 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
809 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
810 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x1),
811 &ccm_anatop->pll_video_set);
814 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
815 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
816 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x3),
817 &ccm_anatop->pll_video_set);
821 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
822 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x2) |
823 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
824 &ccm_anatop->pll_video_set);
828 writel(CCM_ANALOG_PLL_VIDEO_NUM_A(pll_num),
829 &ccm_anatop->pll_video_num);
831 writel(CCM_ANALOG_PLL_VIDEO_DENOM_B(pll_denom),
832 &ccm_anatop->pll_video_denom);
835 start = get_timer(0); /* Get current timestamp */
838 reg = readl(&ccm_anatop->pll_video);
839 if (reg & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) {
841 writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK,
842 &ccm_anatop->pll_video_set);
845 } while (get_timer(0) < (start + 10)); /* Wait 10ms */
847 printf("Lock PLL5 timeout\n");
852 int set_clk_qspi(void)
856 /* disable the clock gate first */
857 clock_enable(CCGR_QSPI, 0);
860 target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
861 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
862 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
863 clock_set_target_val(QSPI_CLK_ROOT, target);
865 /* enable the clock gate */
866 clock_enable(CCGR_QSPI, 1);
871 int set_clk_nand(void)
875 /* disable the clock gate first */
876 clock_enable(CCGR_RAWNAND, 0);
880 target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK |
881 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
882 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV5);
883 clock_set_target_val(NAND_CLK_ROOT, target);
885 /* enable the clock gate */
886 clock_enable(CCGR_RAWNAND, 1);
891 void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
893 u32 hck = MXC_HCLK/1000;
897 u32 i, j, pred = 1, postd = 1;
898 u32 pll_div, pll_num, pll_denom, post_div = 0;
901 debug("mxs_set_lcdclk, freq = %d\n", freq);
903 clock_enable(CCGR_LCDIF, 0);
905 temp = (freq * 8 * 8);
907 for (i = 1; i <= 4; i++) {
908 if ((temp * (1 << i)) > min) {
910 freq = (freq * (1 << i));
916 printf("Fail to set rate to %dkhz", freq);
921 for (i = 1; i <= 8; i++) {
922 for (j = 1; j <= 8; j++) {
924 if (temp > max || temp < min)
927 if (best == 0 || temp < best) {
936 printf("Fail to set rate to %dkhz", freq);
940 debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
942 pll_div = best / hck;
944 pll_num = (best - hck * pll_div) * pll_denom / hck;
946 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
949 target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK |
950 CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1));
951 clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target);
953 clock_enable(CCGR_LCDIF, 1);
956 #ifdef CONFIG_FEC_MXC
957 int set_clk_enet(enum enet_freq type)
961 u32 enet1_ref, enet2_ref;
963 /* disable the clock first */
964 clock_enable(CCGR_ENET1, 0);
965 clock_enable(CCGR_ENET2, 0);
969 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
970 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
973 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
974 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
977 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
978 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
984 ret = enable_pll_enet();
988 /* set enet axi clock 196M: 392/2 */
989 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
990 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
991 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
992 clock_set_target_val(ENET_AXI_CLK_ROOT, target);
994 target = CLK_ROOT_ON | enet1_ref |
995 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
996 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
997 clock_set_target_val(ENET1_REF_CLK_ROOT, target);
999 target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
1000 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1001 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
1002 clock_set_target_val(ENET1_TIME_CLK_ROOT, target);
1004 target = CLK_ROOT_ON | enet2_ref |
1005 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1006 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
1007 clock_set_target_val(ENET2_REF_CLK_ROOT, target);
1009 target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
1010 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1011 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
1012 clock_set_target_val(ENET2_TIME_CLK_ROOT, target);
1014 #ifdef CONFIG_FEC_MXC_25M_REF_CLK
1015 target = CLK_ROOT_ON |
1016 ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
1017 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1018 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
1019 clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
1022 clock_enable(CCGR_ENET1, 1);
1023 clock_enable(CCGR_ENET2, 1);
1029 /* Configure PLL/PFD freq */
1030 void clock_init(void)
1032 /* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
1033 * In u-boot, we have to:
1034 * 1. Configure PFD3- PFD7 for freq we needed in u-boot
1035 * 2. Set clock root for peripherals (ip channel) used in u-boot but without set rate
1036 * interface. The clocks for these peripherals are enabled after this intialization.
1037 * 3. Other peripherals with set clock rate interface does not be set in this function.
1042 * Configure PFD4 to 392M
1043 * 480M * 18 / 0x16 = 392M
1045 reg = readl(&ccm_anatop->pfd_480b);
1047 reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK |
1048 CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK);
1049 reg |= ANATOP_PFD480B_PFD4_FRAC_392M_VAL;
1051 writel(reg, &ccm_anatop->pfd_480b);
1058 #ifdef CONFIG_MXC_EPDC
1062 enable_usboh3_clk(1);
1064 clock_enable(CCGR_SNVS, 1);
1066 #ifdef CONFIG_NAND_MXS
1067 clock_enable(CCGR_RAWNAND, 1);
1070 if (IS_ENABLED(CONFIG_IMX_RDC)) {
1071 clock_enable(CCGR_RDC, 1);
1072 clock_enable(CCGR_SEMA1, 1);
1073 clock_enable(CCGR_SEMA2, 1);
1077 #ifdef CONFIG_SECURE_BOOT
1078 void hab_caam_clock_enable(unsigned char enable)
1081 clock_enable(CCGR_CAAM, 1);
1083 clock_enable(CCGR_CAAM, 0);
1087 #ifdef CONFIG_MXC_EPDC
1088 void epdc_clock_enable(void)
1090 clock_enable(CCGR_EPDC, 1);
1092 void epdc_clock_disable(void)
1094 clock_enable(CCGR_EPDC, 0);
1098 #ifndef CONFIG_SPL_BUILD
1100 * Dump some core clockes.
1102 int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1105 freq = decode_pll(PLL_CORE, MXC_HCLK);
1106 printf("PLL_CORE %8d MHz\n", freq / 1000000);
1107 freq = decode_pll(PLL_SYS, MXC_HCLK);
1108 printf("PLL_SYS %8d MHz\n", freq / 1000000);
1109 freq = decode_pll(PLL_ENET, MXC_HCLK);
1110 printf("PLL_NET %8d MHz\n", freq / 1000000);
1114 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
1115 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
1116 #ifdef CONFIG_MXC_SPI
1117 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
1119 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
1120 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
1121 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
1122 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
1123 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
1124 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
1130 clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,