3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/dma.h>
18 #include <asm/mach-imx/hab.h>
20 #include <asm/arch/mxc_hdmi.h>
21 #include <asm/arch/crm_regs.h>
23 #include <imx_thermal.h>
40 #if defined(CONFIG_IMX_THERMAL)
41 static const struct imx_thermal_plat imx6_thermal_plat = {
42 .regs = (void *)ANATOP_BASE_ADDR,
47 U_BOOT_DEVICE(imx6_thermal) = {
48 .name = "imx_thermal",
49 .platdata = &imx6_thermal_plat,
53 #if defined(CONFIG_SECURE_BOOT)
54 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
62 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
63 return readl(&scu->config) & 3;
68 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
69 u32 reg = readl(&anatop->digprog_sololite);
70 u32 type = ((reg >> 16) & 0xff);
73 if (type != MXC_CPU_MX6SL) {
74 reg = readl(&anatop->digprog);
75 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
76 cfg = readl(&scu->config) & 3;
77 type = ((reg >> 16) & 0xff);
78 if (type == MXC_CPU_MX6DL) {
80 type = MXC_CPU_MX6SOLO;
83 if (type == MXC_CPU_MX6Q) {
89 major = ((reg >> 8) & 0xff);
91 ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
97 reg &= 0xff; /* mx6 silicon revision */
98 return (type << 12) | (reg + (0x10 * (major + 1)));
102 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
103 * defines a 2-bit SPEED_GRADING
105 #define OCOTP_CFG3_SPEED_SHIFT 16
106 #define OCOTP_CFG3_SPEED_800MHZ 0
107 #define OCOTP_CFG3_SPEED_850MHZ 1
108 #define OCOTP_CFG3_SPEED_1GHZ 2
109 #define OCOTP_CFG3_SPEED_1P2GHZ 3
114 #define OCOTP_CFG3_SPEED_528MHZ 1
115 #define OCOTP_CFG3_SPEED_696MHZ 2
120 #define OCOTP_CFG3_SPEED_792MHZ 2
121 #define OCOTP_CFG3_SPEED_900MHZ 3
123 u32 get_cpu_speed_grade_hz(void)
125 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
126 struct fuse_bank *bank = &ocotp->bank[0];
127 struct fuse_bank0_regs *fuse =
128 (struct fuse_bank0_regs *)bank->fuse_regs;
131 val = readl(&fuse->cfg3);
132 val >>= OCOTP_CFG3_SPEED_SHIFT;
136 if (val == OCOTP_CFG3_SPEED_528MHZ)
138 else if (val == OCOTP_CFG3_SPEED_696MHZ)
145 if (val == OCOTP_CFG3_SPEED_528MHZ)
147 else if (val == OCOTP_CFG3_SPEED_792MHZ)
149 else if (val == OCOTP_CFG3_SPEED_900MHZ)
156 /* Valid for IMX6DQ */
157 case OCOTP_CFG3_SPEED_1P2GHZ:
158 if (is_mx6dq() || is_mx6dqp())
160 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
161 case OCOTP_CFG3_SPEED_1GHZ:
163 /* Valid for IMX6DQ */
164 case OCOTP_CFG3_SPEED_850MHZ:
165 if (is_mx6dq() || is_mx6dqp())
167 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
168 case OCOTP_CFG3_SPEED_800MHZ:
175 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
176 * defines a 2-bit Temperature Grade
178 * return temperature grade and min/max temperature in Celsius
180 #define OCOTP_MEM0_TEMP_SHIFT 6
182 u32 get_cpu_temp_grade(int *minc, int *maxc)
184 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
185 struct fuse_bank *bank = &ocotp->bank[1];
186 struct fuse_bank1_regs *fuse =
187 (struct fuse_bank1_regs *)bank->fuse_regs;
190 val = readl(&fuse->mem0);
191 val >>= OCOTP_MEM0_TEMP_SHIFT;
195 if (val == TEMP_AUTOMOTIVE) {
198 } else if (val == TEMP_INDUSTRIAL) {
201 } else if (val == TEMP_EXTCOMMERCIAL) {
212 #ifdef CONFIG_REVISION_TAG
213 u32 __weak get_board_rev(void)
215 u32 cpurev = get_cpu_rev();
216 u32 type = ((cpurev >> 12) & 0xff);
217 if (type == MXC_CPU_MX6SOLO)
218 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
220 if (type == MXC_CPU_MX6D)
221 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
227 static void clear_ldo_ramp(void)
229 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
232 /* ROM may modify LDO ramp up time according to fuse setting, so in
233 * order to be in the safe side we neeed to reset these settings to
234 * match the reset value: 0'b00
236 reg = readl(&anatop->ana_misc2);
237 reg &= ~(0x3f << 24);
238 writel(reg, &anatop->ana_misc2);
242 * Set the PMU_REG_CORE register
244 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
245 * Possible values are from 0.725V to 1.450V in steps of
248 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
250 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
251 u32 val, step, old, reg = readl(&anatop->reg_core);
254 /* No LDO_SOC/PU/ARM */
259 val = 0x00; /* Power gated off */
261 val = 0x1F; /* Power FET switched full on. No regulation */
263 val = (mv - 700) / 25;
281 old = (reg & (0x1F << shift)) >> shift;
282 step = abs(val - old);
286 reg = (reg & ~(0x1F << shift)) | (val << shift);
287 writel(reg, &anatop->reg_core);
290 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
298 static void set_ahb_rate(u32 val)
300 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
303 div = get_periph_clk() / val - 1;
304 reg = readl(&mxc_ccm->cbcdr);
306 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
307 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
310 static void clear_mmdc_ch_mask(void)
312 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
314 reg = readl(&mxc_ccm->ccdr);
316 /* Clear MMDC channel mask */
317 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll())
318 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
320 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
321 writel(reg, &mxc_ccm->ccdr);
324 #define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
326 static void init_bandgap(void)
328 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
329 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
330 struct fuse_bank *bank = &ocotp->bank[1];
331 struct fuse_bank1_regs *fuse =
332 (struct fuse_bank1_regs *)bank->fuse_regs;
336 * Ensure the bandgap has stabilized.
338 while (!(readl(&anatop->ana_misc0) & 0x80))
341 * For best noise performance of the analog blocks using the
342 * outputs of the bandgap, the reftop_selfbiasoff bit should
345 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
347 * On i.MX6ULL,we need to set VBGADJ bits according to the
348 * REFTOP_TRIM[3:0] in fuse table
349 * 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
350 * 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
351 * 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
352 * 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
353 * 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
354 * 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
355 * 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
356 * 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
359 val = readl(&fuse->mem0);
360 val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
363 writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
364 &anatop->ana_misc0_set);
368 int arch_cpu_init(void)
370 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
374 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
375 clear_mmdc_ch_mask();
378 * Disable self-bias circuit in the analog bandap.
379 * The self-bias circuit is used by the bandgap during startup.
380 * This bit should be set after the bandgap has initialized.
384 if (!is_mx6ul() && !is_mx6ull()) {
386 * When low freq boot is enabled, ROM will not set AHB
387 * freq, so we need to ensure AHB freq is 132MHz in such
390 * To i.MX6UL, when power up, default ARM core and
391 * AHB rate is 396M and 132M.
393 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
394 set_ahb_rate(132000000);
398 if (is_soc_rev(CHIP_REV_1_0) == 0) {
400 * According to the design team's requirement on
401 * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
402 * as open drain 100K (0x0000b8a0).
403 * Only exists on TO1.0
405 writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
408 * From TO1.1, SNVS adds internal pull up control
409 * for POR_B, the register filed is GPBIT[1:0],
410 * after system boot up, it can be set to 2b'01
411 * to disable internal pull up.It can save about
412 * 30uA power in SNVS mode.
414 writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
416 MX6UL_SNVS_LP_BASE_ADDR + 0x10);
422 * GPBIT[1:0] is suggested to set to 2'b11:
423 * 2'b00 : always PUP100K
424 * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
425 * 2'b10 : always disable PUP100K
426 * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
427 * register offset is different from i.MX6UL, since
428 * i.MX6UL is fixed by ECO.
430 writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
431 0x3, MX6UL_SNVS_LP_BASE_ADDR);
434 /* Set perclk to source from OSC 24MHz */
436 setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
438 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
441 setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
448 #ifdef CONFIG_ENV_IS_IN_MMC
449 __weak int board_mmc_get_env_dev(int devno)
451 return CONFIG_SYS_MMC_ENV_DEV;
454 static int mmc_get_boot_dev(void)
456 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
457 u32 soc_sbmr = readl(&src_regs->sbmr1);
463 * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
464 * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
465 * i.MX6SL/SX/UL has same layout.
467 bootsel = (soc_sbmr & 0x000000FF) >> 6;
469 /* No boot from sd/mmc */
473 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
474 devno = (soc_sbmr & 0x00001800) >> 11;
479 int mmc_get_env_dev(void)
481 int devno = mmc_get_boot_dev();
483 /* If not boot from sd/mmc, use default value */
485 return CONFIG_SYS_MMC_ENV_DEV;
487 return board_mmc_get_env_dev(devno);
490 #ifdef CONFIG_SYS_MMC_ENV_PART
491 __weak int board_mmc_get_env_part(int devno)
493 return CONFIG_SYS_MMC_ENV_PART;
496 uint mmc_get_env_part(struct mmc *mmc)
498 int devno = mmc_get_boot_dev();
500 /* If not boot from sd/mmc, use default value */
502 return CONFIG_SYS_MMC_ENV_PART;
504 return board_mmc_get_env_part(devno);
509 int board_postclk_init(void)
511 /* NO LDO SOC on i.MX6SLL */
515 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
520 #if defined(CONFIG_FEC_MXC)
521 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
523 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
524 struct fuse_bank *bank = &ocotp->bank[4];
525 struct fuse_bank4_regs *fuse =
526 (struct fuse_bank4_regs *)bank->fuse_regs;
528 if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) {
529 u32 value = readl(&fuse->mac_addr2);
530 mac[0] = value >> 24 ;
531 mac[1] = value >> 16 ;
532 mac[2] = value >> 8 ;
535 value = readl(&fuse->mac_addr1);
536 mac[4] = value >> 24 ;
537 mac[5] = value >> 16 ;
540 u32 value = readl(&fuse->mac_addr1);
541 mac[0] = (value >> 8);
544 value = readl(&fuse->mac_addr0);
545 mac[2] = value >> 24 ;
546 mac[3] = value >> 16 ;
547 mac[4] = value >> 8 ;
554 #ifndef CONFIG_SPL_BUILD
556 * cfg_val will be used for
557 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
558 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
559 * instead of SBMR1 to determine the boot device.
561 const struct boot_mode soc_boot_modes[] = {
562 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
563 /* reserved value should start rom usb */
564 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
565 {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
567 {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
569 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
570 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
571 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
572 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
573 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
574 /* 4 bit bus width */
575 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
576 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
577 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
578 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
583 void reset_misc(void)
585 #ifdef CONFIG_VIDEO_MXS
592 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
593 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
596 u32 reg, periph1, periph2;
598 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
601 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
602 * to make sure PFD is working right, otherwise, PFDs may
603 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
604 * workaround in ROM code, as bus clock need it
607 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
608 ANATOP_PFD_CLKGATE_MASK(1) |
609 ANATOP_PFD_CLKGATE_MASK(2) |
610 ANATOP_PFD_CLKGATE_MASK(3);
611 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
612 ANATOP_PFD_CLKGATE_MASK(3);
614 reg = readl(&ccm->cbcmr);
615 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
616 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
617 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
618 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
620 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
621 if ((periph2 != 0x2) && (periph1 != 0x2))
622 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
624 if ((periph2 != 0x1) && (periph1 != 0x1) &&
625 (periph2 != 0x3) && (periph1 != 0x3))
626 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
628 writel(mask480, &anatop->pfd_480_set);
629 writel(mask528, &anatop->pfd_528_set);
630 writel(mask480, &anatop->pfd_480_clr);
631 writel(mask528, &anatop->pfd_528_clr);
634 #ifdef CONFIG_IMX_HDMI
635 void imx_enable_hdmi_phy(void)
637 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
639 reg = readb(&hdmi->phy_conf0);
640 reg |= HDMI_PHY_CONF0_PDZ_MASK;
641 writeb(reg, &hdmi->phy_conf0);
643 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
644 writeb(reg, &hdmi->phy_conf0);
646 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
647 writeb(reg, &hdmi->phy_conf0);
648 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
651 void imx_setup_hdmi(void)
653 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
654 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
658 /* Turn on HDMI PHY clock */
659 reg = readl(&mxc_ccm->CCGR2);
660 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
661 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
662 writel(reg, &mxc_ccm->CCGR2);
663 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
664 reg = readl(&mxc_ccm->chsccdr);
665 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
666 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
667 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
668 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
669 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
670 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
671 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
672 writel(reg, &mxc_ccm->chsccdr);
674 /* Clear the overflow condition */
675 if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
676 /* TMDS software reset */
677 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
678 val = readb(&hdmi->fc_invidconf);
679 /* Need minimum 3 times to write to clear the register */
680 for (count = 0 ; count < 5 ; count++)
681 writeb(val, &hdmi->fc_invidconf);
688 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
690 /* enable AXI cache for VDOA/VPU/IPU */
691 writel(0xF00000CF, &iomux->gpr[4]);
693 /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
694 writel(0x77177717, &iomux->gpr[6]);
695 writel(0x77177717, &iomux->gpr[7]);
697 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
698 writel(0x007F007F, &iomux->gpr[6]);
699 writel(0x007F007F, &iomux->gpr[7]);
703 #ifdef CONFIG_IMX_BOOTAUX
704 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
709 if (!boot_private_data)
712 stack = *(u32 *)boot_private_data;
713 pc = *(u32 *)(boot_private_data + 4);
715 /* Set the stack and pc to M4 bootROM */
716 writel(stack, M4_BOOTROM_BASE_ADDR);
717 writel(pc, M4_BOOTROM_BASE_ADDR + 4);
720 src_reg = (struct src *)SRC_BASE_ADDR;
721 clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK,
722 SRC_SCR_M4_ENABLE_MASK);
727 int arch_auxiliary_core_check_up(u32 core_id)
729 struct src *src_reg = (struct src *)SRC_BASE_ADDR;
732 val = readl(&src_reg->scr);
734 if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK)
735 return 0; /* assert in reset */