2 * Copyright (C) 2018 Armadeus Systems
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/clock.h>
8 #include <asm/arch/crm_regs.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <asm/arch/sys_proto.h>
14 #include <asm/mach-imx/iomux-v3.h>
17 #include <environment.h>
19 DECLARE_GLOBAL_DATA_PTR;
24 #define MDIO_PAD_CTRL ( \
25 PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
29 #define ENET_PAD_CTRL_PU ( \
30 PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
34 #define ENET_PAD_CTRL_PD ( \
35 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
39 #define ENET_CLK_PAD_CTRL ( \
40 PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
41 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \
44 static iomux_v3_cfg_t const fec1_pads[] = {
45 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
46 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
47 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
48 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
49 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
50 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
51 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
52 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
53 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
55 MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
57 MX6_PAD_NAND_DATA00__GPIO4_IO02 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
58 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
61 int board_phy_config(struct phy_device *phydev)
63 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
65 if (phydev->drv->config)
66 phydev->drv->config(phydev);
71 int board_eth_init(bd_t *bis)
73 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
77 /* Use 50M anatop loopback REF_CLK1 for ENET1,
78 * clear gpr1[13], set gpr1[17] */
79 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
80 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
82 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
88 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
90 ret = dm_gpio_lookup_name("GPIO4_2", &rst);
92 printf("Cannot get GPIO4_2\n");
96 ret = dm_gpio_request(&rst, "phy-rst");
98 printf("Cannot request GPIO4_2\n");
102 dm_gpio_set_dir_flags(&rst, GPIOD_IS_OUT);
103 dm_gpio_set_value(&rst, 0);
105 dm_gpio_set_value(&rst, 1);
107 return fecmxc_initialize(bis);
109 #endif /* CONFIG_FEC_MXC */
113 /* Address of boot parameters */
114 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
119 int __weak opos6ul_board_late_init(void)
124 int board_late_init(void)
126 struct src *psrc = (struct src *)SRC_BASE_ADDR;
127 unsigned reg = readl(&psrc->sbmr2);
129 /* In bootstrap don't use the env vars */
130 if (((reg & 0x3000000) >> 24) == 0x1) {
131 set_default_env(NULL);
132 env_set("preboot", "");
135 return opos6ul_board_late_init();
140 gd->ram_size = imx_ddr_size();
145 #ifdef CONFIG_SPL_BUILD
146 #include <asm/arch/mx6-ddr.h>
147 #include <linux/libfdt.h>
150 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
151 .grp_addds = 0x00000030,
152 .grp_ddrmode_ctl = 0x00020000,
153 .grp_b0ds = 0x00000030,
154 .grp_ctlds = 0x00000030,
155 .grp_b1ds = 0x00000030,
156 .grp_ddrpke = 0x00000000,
157 .grp_ddrmode = 0x00020000,
158 .grp_ddr_type = 0x000c0000,
161 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
162 .dram_dqm0 = 0x00000030,
163 .dram_dqm1 = 0x00000030,
164 .dram_ras = 0x00000030,
165 .dram_cas = 0x00000030,
166 .dram_odt0 = 0x00000030,
167 .dram_odt1 = 0x00000030,
168 .dram_sdba2 = 0x00000000,
169 .dram_sdclk_0 = 0x00000008,
170 .dram_sdqs0 = 0x00000038,
171 .dram_sdqs1 = 0x00000030,
172 .dram_reset = 0x00000030,
175 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
176 .p0_mpwldectrl0 = 0x00070007,
177 .p0_mpdgctrl0 = 0x41490145,
178 .p0_mprddlctl = 0x40404546,
179 .p0_mpwrdlctl = 0x4040524D,
182 struct mx6_ddr_sysinfo ddr_sysinfo = {
188 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
189 .walat = 1, /* Write additional latency */
190 .ralat = 5, /* Read additional latency */
191 .mif3_mode = 3, /* Command prediction working mode */
192 .bi_on = 1, /* Bank interleaving enabled */
193 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
194 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
195 .ddr_type = DDR_TYPE_DDR3,
198 static struct mx6_ddr3_cfg mem_ddr = {
211 static void ccgr_init(void)
213 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
215 writel(0xFFFFFFFF, &ccm->CCGR0);
216 writel(0xFFFFFFFF, &ccm->CCGR1);
217 writel(0xFFFFFFFF, &ccm->CCGR2);
218 writel(0xFFFFFFFF, &ccm->CCGR3);
219 writel(0xFFFFFFFF, &ccm->CCGR4);
220 writel(0xFFFFFFFF, &ccm->CCGR5);
221 writel(0xFFFFFFFF, &ccm->CCGR6);
222 writel(0xFFFFFFFF, &ccm->CCGR7);
225 static void spl_dram_init(void)
227 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
228 struct fuse_bank *bank = &ocotp->bank[4];
229 struct fuse_bank4_regs *fuse =
230 (struct fuse_bank4_regs *)bank->fuse_regs;
231 int reg = readl(&fuse->gp1);
236 mem_ddr.rowaddr = 15;
238 mem_ddr.trcmin = 4875;
239 mem_ddr.trasmin = 3500;
242 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
243 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
246 void spl_board_init(void)
248 preloader_console_init();
251 void board_init_f(ulong dummy)
255 /* setup AIPS and disable watchdog */
261 /* DDR initialization */
264 #endif /* CONFIG_SPL_BUILD */