2 * Copyright (C) 2017 Armadeus Systems
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/clock.h>
8 #include <asm/arch/crm_regs.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <asm/arch/mx6ul_pins.h>
13 #include <asm/arch/sys_proto.h>
15 #include <asm/mach-imx/iomux-v3.h>
18 #include <environment.h>
19 #include <fsl_esdhc.h>
22 DECLARE_GLOBAL_DATA_PTR;
27 #define MDIO_PAD_CTRL ( \
28 PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
32 #define ENET_PAD_CTRL_PU ( \
33 PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
37 #define ENET_PAD_CTRL_PD ( \
38 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
42 #define ENET_CLK_PAD_CTRL ( \
43 PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
44 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \
47 static iomux_v3_cfg_t const fec1_pads[] = {
48 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
49 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
50 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
51 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
52 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
53 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
54 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
55 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
56 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
58 MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
60 MX6_PAD_NAND_DATA00__GPIO4_IO02 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
61 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
64 int board_phy_config(struct phy_device *phydev)
66 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
68 if (phydev->drv->config)
69 phydev->drv->config(phydev);
74 int board_eth_init(bd_t *bis)
76 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
80 /* Use 50M anatop loopback REF_CLK1 for ENET1,
81 * clear gpr1[13], set gpr1[17] */
82 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
83 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
85 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
91 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
93 ret = dm_gpio_lookup_name("GPIO4_2", &rst);
95 printf("Cannot get GPIO4_2\n");
99 ret = dm_gpio_request(&rst, "phy-rst");
101 printf("Cannot request GPIO4_2\n");
105 dm_gpio_set_dir_flags(&rst, GPIOD_IS_OUT);
106 dm_gpio_set_value(&rst, 0);
108 dm_gpio_set_value(&rst, 1);
110 return fecmxc_initialize(bis);
112 #endif /* CONFIG_FEC_MXC */
116 /* Address of boot parameters */
117 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
122 int __weak opos6ul_board_late_init(void)
127 int board_late_init(void)
129 struct src *psrc = (struct src *)SRC_BASE_ADDR;
130 unsigned reg = readl(&psrc->sbmr2);
132 /* In bootstrap don't use the env vars */
133 if (((reg & 0x3000000) >> 24) == 0x1) {
134 set_default_env(NULL);
135 env_set("preboot", "");
138 return opos6ul_board_late_init();
141 int board_mmc_getcd(struct mmc *mmc)
143 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
144 return cfg->esdhc_base == USDHC1_BASE_ADDR;
149 gd->ram_size = imx_ddr_size();
154 #ifdef CONFIG_SPL_BUILD
155 #include <asm/arch/mx6-ddr.h>
156 #include <asm/arch/opos6ul.h>
160 #define USDHC_PAD_CTRL ( \
161 PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \
162 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST \
165 struct fsl_esdhc_cfg usdhc_cfg[1] = {
166 {USDHC1_BASE_ADDR, 0, 8},
169 static iomux_v3_cfg_t const usdhc1_pads[] = {
170 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
171 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
172 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
173 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
174 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
175 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
176 MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
177 MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
178 MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
179 MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
182 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
183 .grp_addds = 0x00000030,
184 .grp_ddrmode_ctl = 0x00020000,
185 .grp_b0ds = 0x00000030,
186 .grp_ctlds = 0x00000030,
187 .grp_b1ds = 0x00000030,
188 .grp_ddrpke = 0x00000000,
189 .grp_ddrmode = 0x00020000,
190 .grp_ddr_type = 0x000c0000,
193 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
194 .dram_dqm0 = 0x00000030,
195 .dram_dqm1 = 0x00000030,
196 .dram_ras = 0x00000030,
197 .dram_cas = 0x00000030,
198 .dram_odt0 = 0x00000030,
199 .dram_odt1 = 0x00000030,
200 .dram_sdba2 = 0x00000000,
201 .dram_sdclk_0 = 0x00000008,
202 .dram_sdqs0 = 0x00000038,
203 .dram_sdqs1 = 0x00000030,
204 .dram_reset = 0x00000030,
207 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
208 .p0_mpwldectrl0 = 0x00070007,
209 .p0_mpdgctrl0 = 0x41490145,
210 .p0_mprddlctl = 0x40404546,
211 .p0_mpwrdlctl = 0x4040524D,
214 struct mx6_ddr_sysinfo ddr_sysinfo = {
220 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
221 .walat = 1, /* Write additional latency */
222 .ralat = 5, /* Read additional latency */
223 .mif3_mode = 3, /* Command prediction working mode */
224 .bi_on = 1, /* Bank interleaving enabled */
225 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
226 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
227 .ddr_type = DDR_TYPE_DDR3,
230 static struct mx6_ddr3_cfg mem_ddr = {
243 int board_mmc_init(bd_t *bis)
245 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
246 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
247 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
250 static void ccgr_init(void)
252 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
254 writel(0xFFFFFFFF, &ccm->CCGR0);
255 writel(0xFFFFFFFF, &ccm->CCGR1);
256 writel(0xFFFFFFFF, &ccm->CCGR2);
257 writel(0xFFFFFFFF, &ccm->CCGR3);
258 writel(0xFFFFFFFF, &ccm->CCGR4);
259 writel(0xFFFFFFFF, &ccm->CCGR5);
260 writel(0xFFFFFFFF, &ccm->CCGR6);
261 writel(0xFFFFFFFF, &ccm->CCGR7);
264 static void spl_dram_init(void)
266 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
267 struct fuse_bank *bank = &ocotp->bank[4];
268 struct fuse_bank4_regs *fuse =
269 (struct fuse_bank4_regs *)bank->fuse_regs;
270 int reg = readl(&fuse->gp1);
275 mem_ddr.rowaddr = 15;
277 mem_ddr.trcmin = 4875;
278 mem_ddr.trasmin = 3500;
281 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
282 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
285 void board_init_f(ulong dummy)
289 /* setup AIPS and disable watchdog */
295 /* UART clocks enabled and gd valid - init serial console */
296 opos6ul_setup_uart_debug();
297 preloader_console_init();
299 /* DDR initialization */
302 #endif /* CONFIG_SPL_BUILD */