1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Armadeus Systems
7 #include <asm/arch/clock.h>
8 #include <asm/arch/crm_regs.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/sys_proto.h>
15 DECLARE_GLOBAL_DATA_PTR;
20 int board_phy_config(struct phy_device *phydev)
22 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
24 if (phydev->drv->config)
25 phydev->drv->config(phydev);
30 static int setup_fec(void)
32 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
34 /* Use 50M anatop loopback REF_CLK1 for ENET1,
35 * clear gpr1[13], set gpr1[17] */
36 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
37 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
39 return enable_fec_anatop_clock(0, ENET_50MHZ);
41 #endif /* CONFIG_FEC_MXC */
45 /* Address of boot parameters */
46 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
55 int __weak opos6ul_board_late_init(void)
60 int board_late_init(void)
62 struct src *psrc = (struct src *)SRC_BASE_ADDR;
63 unsigned reg = readl(&psrc->sbmr2);
65 /* In bootstrap don't use the env vars */
66 if (((reg & 0x3000000) >> 24) == 0x1) {
67 env_set_default(NULL, 0);
68 env_set("preboot", "");
71 return opos6ul_board_late_init();
76 gd->ram_size = imx_ddr_size();
81 #ifdef CONFIG_SPL_BUILD
82 #include <asm/arch/mx6-ddr.h>
83 #include <linux/libfdt.h>
86 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
87 .grp_addds = 0x00000030,
88 .grp_ddrmode_ctl = 0x00020000,
89 .grp_b0ds = 0x00000030,
90 .grp_ctlds = 0x00000030,
91 .grp_b1ds = 0x00000030,
92 .grp_ddrpke = 0x00000000,
93 .grp_ddrmode = 0x00020000,
94 .grp_ddr_type = 0x000c0000,
97 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
98 .dram_dqm0 = 0x00000030,
99 .dram_dqm1 = 0x00000030,
100 .dram_ras = 0x00000030,
101 .dram_cas = 0x00000030,
102 .dram_odt0 = 0x00000030,
103 .dram_odt1 = 0x00000030,
104 .dram_sdba2 = 0x00000000,
105 .dram_sdclk_0 = 0x00000008,
106 .dram_sdqs0 = 0x00000038,
107 .dram_sdqs1 = 0x00000030,
108 .dram_reset = 0x00000030,
111 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
112 .p0_mpwldectrl0 = 0x00070007,
113 .p0_mpdgctrl0 = 0x41490145,
114 .p0_mprddlctl = 0x40404546,
115 .p0_mpwrdlctl = 0x4040524D,
118 struct mx6_ddr_sysinfo ddr_sysinfo = {
124 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
125 .walat = 1, /* Write additional latency */
126 .ralat = 5, /* Read additional latency */
127 .mif3_mode = 3, /* Command prediction working mode */
128 .bi_on = 1, /* Bank interleaving enabled */
129 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
130 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
131 .ddr_type = DDR_TYPE_DDR3,
132 .refsel = 1, /* Refresh cycles at 32KHz */
133 .refr = 7, /* 8 refreshes commands per refresh cycle */
136 static struct mx6_ddr3_cfg mem_ddr = {
149 void board_boot_order(u32 *spl_boot_list)
151 unsigned int bmode = readl(&src_base->sbmr2);
153 if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
154 spl_boot_list[0] = BOOT_DEVICE_UART;
156 spl_boot_list[0] = spl_boot_device();
159 static void ccgr_init(void)
161 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
163 writel(0xFFFFFFFF, &ccm->CCGR0);
164 writel(0xFFFFFFFF, &ccm->CCGR1);
165 writel(0xFFFFFFFF, &ccm->CCGR2);
166 writel(0xFFFFFFFF, &ccm->CCGR3);
167 writel(0xFFFFFFFF, &ccm->CCGR4);
168 writel(0xFFFFFFFF, &ccm->CCGR5);
169 writel(0xFFFFFFFF, &ccm->CCGR6);
170 writel(0xFFFFFFFF, &ccm->CCGR7);
173 static void spl_dram_init(void)
175 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
176 struct fuse_bank *bank = &ocotp->bank[4];
177 struct fuse_bank4_regs *fuse =
178 (struct fuse_bank4_regs *)bank->fuse_regs;
179 int reg = readl(&fuse->gp1);
184 mem_ddr.rowaddr = 15;
186 mem_ddr.trcmin = 4875;
187 mem_ddr.trasmin = 3500;
190 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
191 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
194 void spl_board_init(void)
196 preloader_console_init();
199 void board_init_f(ulong dummy)
203 /* setup AIPS and disable watchdog */
209 /* DDR initialization */
212 #endif /* CONFIG_SPL_BUILD */