1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright (C) 2016 Grinn
8 #include <asm/arch/clock.h>
9 #include <asm/arch/iomux.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/mx6ul_pins.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/boot_mode.h>
20 #include <fsl_esdhc_imx.h>
21 #include <linux/delay.h>
22 #include <linux/sizes.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
28 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
29 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
33 gd->ram_size = imx_ddr_size();
38 static iomux_v3_cfg_t const emmc_pads[] = {
39 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
40 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
41 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
42 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
43 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
44 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
45 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
46 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
47 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
48 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
51 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
54 #ifdef CONFIG_FSL_ESDHC_IMX
55 static struct fsl_esdhc_cfg emmc_cfg = {USDHC2_BASE_ADDR, 0, 8};
57 #define EMMC_PWR_GPIO IMX_GPIO_NR(4, 10)
59 int litesom_mmc_init(bd_t *bis)
64 imx_iomux_v3_setup_multiple_pads(emmc_pads, ARRAY_SIZE(emmc_pads));
65 gpio_direction_output(EMMC_PWR_GPIO, 0);
67 gpio_direction_output(EMMC_PWR_GPIO, 1);
68 emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
70 ret = fsl_esdhc_initialize(bis, &emmc_cfg);
72 printf("Warning: failed to initialize mmc dev 1 (eMMC)\n");
80 #ifdef CONFIG_SPL_BUILD
81 #include <linux/libfdt.h>
83 #include <asm/arch/mx6-ddr.h>
86 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
87 .grp_addds = 0x00000030,
88 .grp_ddrmode_ctl = 0x00020000,
89 .grp_b0ds = 0x00000030,
90 .grp_ctlds = 0x00000030,
91 .grp_b1ds = 0x00000030,
92 .grp_ddrpke = 0x00000000,
93 .grp_ddrmode = 0x00020000,
94 .grp_ddr_type = 0x000c0000,
97 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
98 .dram_dqm0 = 0x00000030,
99 .dram_dqm1 = 0x00000030,
100 .dram_ras = 0x00000030,
101 .dram_cas = 0x00000030,
102 .dram_odt0 = 0x00000030,
103 .dram_odt1 = 0x00000030,
104 .dram_sdba2 = 0x00000000,
105 .dram_sdclk_0 = 0x00000030,
106 .dram_sdqs0 = 0x00000030,
107 .dram_sdqs1 = 0x00000030,
108 .dram_reset = 0x00000030,
111 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
112 .p0_mpwldectrl0 = 0x00000000,
113 .p0_mpdgctrl0 = 0x41570155,
114 .p0_mprddlctl = 0x4040474A,
115 .p0_mpwrdlctl = 0x40405550,
118 struct mx6_ddr_sysinfo ddr_sysinfo = {
124 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
125 .walat = 0, /* Write additional latency */
126 .ralat = 5, /* Read additional latency */
127 .mif3_mode = 3, /* Command prediction working mode */
128 .bi_on = 1, /* Bank interleaving enabled */
129 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
130 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
131 .ddr_type = DDR_TYPE_DDR3,
132 .refsel = 0, /* Refresh cycles at 64KHz */
133 .refr = 1, /* 2 refresh commands per refresh cycle */
136 static struct mx6_ddr3_cfg mem_ddr = {
149 static void ccgr_init(void)
151 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
153 writel(0xFFFFFFFF, &ccm->CCGR0);
154 writel(0xFFFFFFFF, &ccm->CCGR1);
155 writel(0xFFFFFFFF, &ccm->CCGR2);
156 writel(0xFFFFFFFF, &ccm->CCGR3);
157 writel(0xFFFFFFFF, &ccm->CCGR4);
158 writel(0xFFFFFFFF, &ccm->CCGR5);
159 writel(0xFFFFFFFF, &ccm->CCGR6);
160 writel(0xFFFFFFFF, &ccm->CCGR7);
163 static void spl_dram_init(void)
165 unsigned long ram_size;
167 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
168 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
171 * Get actual RAM size, so we can adjust DDR row size for <512M
174 ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M);
175 if (ram_size < SZ_512M) {
176 mem_ddr.rowaddr = 14;
177 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
181 void litesom_init_f(void)
185 /* setup AIPS and disable watchdog */
188 #ifdef CONFIG_BOARD_EARLY_INIT_F
189 board_early_init_f();
195 /* UART clocks enabled and gd valid - init serial console */
196 preloader_console_init();
198 /* DDR initialization */