1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
10 #include <linux/delay.h>
11 #include <linux/types.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/mx6-ddr.h>
14 #include <asm/arch/sys_proto.h>
16 #include <asm/types.h>
19 #if defined(CONFIG_MX6_DDRCAL)
20 static void reset_read_data_fifos(void)
22 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
24 /* Reset data FIFOs twice. */
25 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
26 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
28 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
29 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
32 static void precharge_all(const bool cs0_enable, const bool cs1_enable)
34 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
37 * Issue the Precharge-All command to the DDR device for both
38 * chip selects. Note, CON_REQ bit should also remain set. If
39 * only using one chip select, then precharge only the desired
42 if (cs0_enable) { /* CS0 */
43 writel(0x04008050, &mmdc0->mdscr);
44 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
47 if (cs1_enable) { /* CS1 */
48 writel(0x04008058, &mmdc0->mdscr);
49 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
53 static void force_delay_measurement(int bus_size)
55 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
56 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
58 writel(0x800, &mmdc0->mpmur0);
60 writel(0x800, &mmdc1->mpmur0);
63 static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl)
65 u32 dg_tmp_val, dg_dl_abs_offset, dg_hc_del, val_ctrl;
68 * DQS gating absolute offset should be modified from reflecting
69 * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80)
72 val_ctrl = readl(reg_ctrl);
73 val_ctrl &= 0xf0000000;
75 dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0;
76 dg_dl_abs_offset = dg_tmp_val & 0x7f;
77 dg_hc_del = (dg_tmp_val & 0x780) << 1;
79 val_ctrl |= dg_dl_abs_offset + dg_hc_del;
81 dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0;
82 dg_dl_abs_offset = dg_tmp_val & 0x7f;
83 dg_hc_del = (dg_tmp_val & 0x780) << 1;
85 val_ctrl |= (dg_dl_abs_offset + dg_hc_del) << 16;
87 writel(val_ctrl, reg_ctrl);
90 static void correct_mpwldectr_result(void *reg)
92 /* Limit is 200/256 of CK, which is WL_HC_DELx | 0x48. */
93 const unsigned int limit = 0x148;
97 if ((val & 0x17f) > limit)
100 if (((val >> 16) & 0x17f) > limit)
107 int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
109 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
110 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
111 u32 esdmisc_val, zq_val;
113 u32 ldectrl[4] = {0};
118 * Stash old values in case calibration fails,
119 * we need to restore them
121 ldectrl[0] = readl(&mmdc0->mpwldectrl0);
122 ldectrl[1] = readl(&mmdc0->mpwldectrl1);
123 if (sysinfo->dsize == 2) {
124 ldectrl[2] = readl(&mmdc1->mpwldectrl0);
125 ldectrl[3] = readl(&mmdc1->mpwldectrl1);
128 /* disable DDR logic power down timer */
129 clrbits_le32(&mmdc0->mdpdc, 0xff00);
131 /* disable Adopt power down timer */
132 setbits_le32(&mmdc0->mapsr, 0x1);
134 debug("Starting write leveling calibration.\n");
137 * 2. disable auto refresh and ZQ calibration
138 * before proceeding with Write Leveling calibration
140 esdmisc_val = readl(&mmdc0->mdref);
141 writel(0x0000C000, &mmdc0->mdref);
142 zq_val = readl(&mmdc0->mpzqhwctrl);
143 writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
145 /* 3. increase walat and ralat to maximum */
146 rwalat_max = (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17);
147 setbits_le32(&mmdc0->mdmisc, rwalat_max);
148 if (sysinfo->dsize == 2)
149 setbits_le32(&mmdc1->mdmisc, rwalat_max);
151 * 4 & 5. Configure the external DDR device to enter write-leveling
152 * mode through Load Mode Register command.
154 * Bits[31:16] MR1 value (0x0080 write leveling enable)
155 * Bit[9] set WL_EN to enable MMDC DQS output
156 * Bits[6:4] set CMD bits for Load Mode Register programming
157 * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
159 writel(0x00808231, &mmdc0->mdscr);
161 /* 6. Activate automatic calibration by setting MPWLGCR[HW_WL_EN] */
162 writel(0x00000001, &mmdc0->mpwlgcr);
165 * 7. Upon completion of this process the MMDC de-asserts
166 * the MPWLGCR[HW_WL_EN]
168 wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
171 * 8. check for any errors: check both PHYs for x64 configuration,
172 * if x32, check only PHY0
174 if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
176 if (sysinfo->dsize == 2)
177 if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
180 debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
182 /* check to see if cal failed */
183 if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
184 (readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
185 ((sysinfo->dsize < 2) ||
186 ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
187 (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) {
188 debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.\n");
189 writel(ldectrl[0], &mmdc0->mpwldectrl0);
190 writel(ldectrl[1], &mmdc0->mpwldectrl1);
191 if (sysinfo->dsize == 2) {
192 writel(ldectrl[2], &mmdc1->mpwldectrl0);
193 writel(ldectrl[3], &mmdc1->mpwldectrl1);
198 correct_mpwldectr_result(&mmdc0->mpwldectrl0);
199 correct_mpwldectr_result(&mmdc0->mpwldectrl1);
200 if (sysinfo->dsize == 2) {
201 correct_mpwldectr_result(&mmdc1->mpwldectrl0);
202 correct_mpwldectr_result(&mmdc1->mpwldectrl1);
206 * User should issue MRS command to exit write leveling mode
207 * through Load Mode Register command
209 * Bits[31:16] MR1 value "ddr_mr1" value from initialization
210 * Bit[9] clear WL_EN to disable MMDC DQS output
211 * Bits[6:4] set CMD bits for Load Mode Register programming
212 * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
214 writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr);
216 /* re-enable auto refresh and zq cal */
217 writel(esdmisc_val, &mmdc0->mdref);
218 writel(zq_val, &mmdc0->mpzqhwctrl);
220 debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
221 readl(&mmdc0->mpwldectrl0));
222 debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
223 readl(&mmdc0->mpwldectrl1));
224 if (sysinfo->dsize == 2) {
225 debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
226 readl(&mmdc1->mpwldectrl0));
227 debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
228 readl(&mmdc1->mpwldectrl1));
231 /* We must force a readback of these values, to get them to stick */
232 readl(&mmdc0->mpwldectrl0);
233 readl(&mmdc0->mpwldectrl1);
234 if (sysinfo->dsize == 2) {
235 readl(&mmdc1->mpwldectrl0);
236 readl(&mmdc1->mpwldectrl1);
239 /* enable DDR logic power down timer: */
240 setbits_le32(&mmdc0->mdpdc, 0x00005500);
242 /* Enable Adopt power down timer: */
243 clrbits_le32(&mmdc0->mapsr, 0x1);
246 writel(0, &mmdc0->mdscr);
251 static void mmdc_set_sdqs(bool set)
253 struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux =
254 (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
255 struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux =
256 (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
261 sdqs = (u32)(&mx6sx_ddr_iomux->dram_sdqs0);
264 sdqs = (u32)(&mx6dq_ddr_iomux->dram_sdqs0);
268 for (i = 0; i < sdqs_cnt; i++) {
270 setbits_le32(sdqs + (4 * i), 0x7000);
272 clrbits_le32(sdqs + (4 * i), 0x7000);
276 int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
278 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
279 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
282 bool cs0_enable_initial;
283 bool cs1_enable_initial;
286 u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */
288 u32 initdelay = 0x40404040;
290 /* check to see which chip selects are enabled */
291 cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000;
292 cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000;
294 /* disable DDR logic power down timer: */
295 clrbits_le32(&mmdc0->mdpdc, 0xff00);
297 /* disable Adopt power down timer: */
298 setbits_le32(&mmdc0->mapsr, 0x1);
300 /* set DQS pull ups */
303 /* Save old RALAT and WALAT values */
304 esdmisc_val = readl(&mmdc0->mdmisc);
306 setbits_le32(&mmdc0->mdmisc,
307 (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
309 /* Disable auto refresh before proceeding with calibration */
310 temp_ref = readl(&mmdc0->mdref);
311 writel(0x0000c000, &mmdc0->mdref);
314 * Per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2,
315 * this also sets the CON_REQ bit.
317 if (cs0_enable_initial)
318 writel(0x00008020, &mmdc0->mdscr);
319 if (cs1_enable_initial)
320 writel(0x00008028, &mmdc0->mdscr);
322 /* poll to make sure the con_ack bit was asserted */
323 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
326 * Check MDMISC register CALIB_PER_CS to see which CS calibration
327 * is targeted to (under normal cases, it should be cleared
328 * as this is the default value, indicating calibration is directed
330 * Disable the other chip select not being target for calibration
331 * to avoid any potential issues. This will get re-enabled at end
334 if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0)
335 clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
337 clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
340 * Check to see which chip selects are now enabled for
341 * the remainder of the calibration.
343 cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
344 cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
346 precharge_all(cs0_enable, cs1_enable);
348 /* Write the pre-defined value into MPPDCMPR1 */
349 writel(pddword, &mmdc0->mppdcmpr1);
352 * Issue a write access to the external DDR device by setting
353 * the bit SW_DUMMY_WR (bit 0) in the MPSWDAR0 and then poll
354 * this bit until it clears to indicate completion of the write access.
356 setbits_le32(&mmdc0->mpswdar0, 1);
357 wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
359 /* Set the RD_DL_ABS# bits to their default values
360 * (will be calibrated later in the read delay-line calibration).
361 * Both PHYs for x64 configuration, if x32, do only PHY0.
363 writel(initdelay, &mmdc0->mprddlctl);
364 if (sysinfo->dsize == 0x2)
365 writel(initdelay, &mmdc1->mprddlctl);
367 /* Force a measurment, for previous delay setup to take effect. */
368 force_delay_measurement(sysinfo->dsize);
371 * ***************************
372 * Read DQS Gating calibration
373 * ***************************
375 debug("Starting Read DQS Gating calibration.\n");
378 * Reset the read data FIFOs (two resets); only need to issue reset
379 * to PHY0 since in x64 mode, the reset will also go to PHY1.
381 reset_read_data_fifos();
384 * Start the automatic read DQS gating calibration process by
385 * asserting MPDGCTRL0[HW_DG_EN] and MPDGCTRL0[DG_CMP_CYC]
386 * and then poll MPDGCTRL0[HW_DG_EN]] until this bit clears
387 * to indicate completion.
388 * Also, ensure that MPDGCTRL0[HW_DG_ERR] is clear to indicate
389 * no errors were seen during calibration.
393 * Set bit 30: chooses option to wait 32 cycles instead of
394 * 16 before comparing read data.
396 setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
397 if (sysinfo->dsize == 2)
398 setbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
400 /* Set bit 28 to start automatic read DQS gating calibration */
401 setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
403 /* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */
404 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
407 * Check to see if any errors were encountered during calibration
408 * (check MPDGCTRL0[HW_DG_ERR]).
409 * Check both PHYs for x64 configuration, if x32, check only PHY0.
411 if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
414 if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
417 /* now disable mpdgctrl0[DG_CMP_CYC] */
418 clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
419 if (sysinfo->dsize == 2)
420 clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
423 * DQS gating absolute offset should be modified from
424 * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
425 * reflecting (HW_DG_UPx - 0x80)
427 modify_dg_result(&mmdc0->mpdghwst0, &mmdc0->mpdghwst1,
429 modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
431 if (sysinfo->dsize == 0x2) {
432 modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
434 modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
437 debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors);
440 * **********************
441 * Read Delay calibration
442 * **********************
444 debug("Starting Read Delay calibration.\n");
446 reset_read_data_fifos();
449 * 4. Issue the Precharge-All command to the DDR device for both
450 * chip selects. If only using one chip select, then precharge
451 * only the desired chip select.
453 precharge_all(cs0_enable, cs1_enable);
456 * 9. Read delay-line calibration
457 * Start the automatic read calibration process by asserting
458 * MPRDDLHWCTL[HW_RD_DL_EN].
460 writel(0x00000030, &mmdc0->mprddlhwctl);
463 * 10. poll for completion
464 * MMDC indicates that the write data calibration had finished by
465 * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that
466 * no error bits were set.
468 wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
470 /* check both PHYs for x64 configuration, if x32, check only PHY0 */
471 if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
474 if ((sysinfo->dsize == 0x2) &&
475 (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
478 debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);
481 * ***********************
482 * Write Delay Calibration
483 * ***********************
485 debug("Starting Write Delay calibration.\n");
487 reset_read_data_fifos();
490 * 4. Issue the Precharge-All command to the DDR device for both
491 * chip selects. If only using one chip select, then precharge
492 * only the desired chip select.
494 precharge_all(cs0_enable, cs1_enable);
497 * 8. Set the WR_DL_ABS# bits to their default values.
498 * Both PHYs for x64 configuration, if x32, do only PHY0.
500 writel(initdelay, &mmdc0->mpwrdlctl);
501 if (sysinfo->dsize == 0x2)
502 writel(initdelay, &mmdc1->mpwrdlctl);
505 * XXX This isn't in the manual. Force a measurement,
506 * for previous delay setup to effect.
508 force_delay_measurement(sysinfo->dsize);
511 * 9. 10. Start the automatic write calibration process
512 * by asserting MPWRDLHWCTL0[HW_WR_DL_EN].
514 writel(0x00000030, &mmdc0->mpwrdlhwctl);
517 * Poll for completion.
518 * MMDC indicates that the write data calibration had finished
519 * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
520 * Also, ensure that no error bits were set.
522 wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
524 /* Check both PHYs for x64 configuration, if x32, check only PHY0 */
525 if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
528 if ((sysinfo->dsize == 0x2) &&
529 (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
532 debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);
534 reset_read_data_fifos();
536 /* Enable DDR logic power down timer */
537 setbits_le32(&mmdc0->mdpdc, 0x00005500);
539 /* Enable Adopt power down timer */
540 clrbits_le32(&mmdc0->mapsr, 0x1);
542 /* Restore MDMISC value (RALAT, WALAT) to MMDCP1 */
543 writel(esdmisc_val, &mmdc0->mdmisc);
545 /* Clear DQS pull ups */
546 mmdc_set_sdqs(false);
548 /* Re-enable SDE (chip selects) if they were set initially */
549 if (cs1_enable_initial)
551 setbits_le32(&mmdc0->mdctl, 1 << 30);
553 if (cs0_enable_initial)
555 setbits_le32(&mmdc0->mdctl, 1 << 31);
557 /* Re-enable to auto refresh */
558 writel(temp_ref, &mmdc0->mdref);
560 /* Clear the MDSCR (including the con_req bit) */
561 writel(0x0, &mmdc0->mdscr); /* CS0 */
563 /* Poll to make sure the con_ack bit is clear */
564 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0);
567 * Print out the registers that were updated as a result
568 * of the calibration process.
570 debug("MMDC registers updated from calibration\n");
571 debug("Read DQS gating calibration:\n");
572 debug("\tMPDGCTRL0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdgctrl0));
573 debug("\tMPDGCTRL1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdgctrl1));
574 if (sysinfo->dsize == 2) {
575 debug("\tMPDGCTRL0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdgctrl0));
576 debug("\tMPDGCTRL1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdgctrl1));
578 debug("Read calibration:\n");
579 debug("\tMPRDDLCTL PHY0 = 0x%08x\n", readl(&mmdc0->mprddlctl));
580 if (sysinfo->dsize == 2)
581 debug("\tMPRDDLCTL PHY1 = 0x%08x\n", readl(&mmdc1->mprddlctl));
582 debug("Write calibration:\n");
583 debug("\tMPWRDLCTL PHY0 = 0x%08x\n", readl(&mmdc0->mpwrdlctl));
584 if (sysinfo->dsize == 2)
585 debug("\tMPWRDLCTL PHY1 = 0x%08x\n", readl(&mmdc1->mpwrdlctl));
588 * Registers below are for debugging purposes. These print out
589 * the upper and lower boundaries captured during
590 * read DQS gating calibration.
592 debug("Status registers bounds for read DQS gating:\n");
593 debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0));
594 debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
595 debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
596 debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
597 if (sysinfo->dsize == 2) {
598 debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
599 debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
600 debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
601 debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
604 debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
610 #if defined(CONFIG_MX6SX)
611 /* Configure MX6SX mmdc iomux */
612 void mx6sx_dram_iocfg(unsigned width,
613 const struct mx6sx_iomux_ddr_regs *ddr,
614 const struct mx6sx_iomux_grp_regs *grp)
616 struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
617 struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
619 mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
620 mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
623 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
624 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
627 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
630 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
631 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
632 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
635 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
636 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
637 writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
638 writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
639 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
640 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
641 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
644 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
645 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
646 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
648 writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
649 writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
653 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
654 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
655 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
657 writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
658 writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
660 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
661 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
663 writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
664 writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
669 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
670 void mx6ul_dram_iocfg(unsigned width,
671 const struct mx6ul_iomux_ddr_regs *ddr,
672 const struct mx6ul_iomux_grp_regs *grp)
674 struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
675 struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
677 mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
678 mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
681 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
682 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
685 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
688 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
689 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
690 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
693 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
694 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
695 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
696 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
697 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
700 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
701 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
702 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
705 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
706 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
707 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
708 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
709 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
713 #if defined(CONFIG_MX6SL)
714 void mx6sl_dram_iocfg(unsigned width,
715 const struct mx6sl_iomux_ddr_regs *ddr,
716 const struct mx6sl_iomux_grp_regs *grp)
718 struct mx6sl_iomux_ddr_regs *mx6_ddr_iomux;
719 struct mx6sl_iomux_grp_regs *mx6_grp_iomux;
721 mx6_ddr_iomux = (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
722 mx6_grp_iomux = (struct mx6sl_iomux_grp_regs *)MX6SL_IOM_GRP_BASE;
725 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
726 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
729 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
732 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
733 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
734 mx6_grp_iomux->grp_addds = grp->grp_addds;
737 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
738 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
739 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
742 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
743 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
744 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
746 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
747 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
751 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
752 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
753 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
755 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
756 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
759 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
760 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
762 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
763 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
768 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
769 /* Configure MX6DQ mmdc iomux */
770 void mx6dq_dram_iocfg(unsigned width,
771 const struct mx6dq_iomux_ddr_regs *ddr,
772 const struct mx6dq_iomux_grp_regs *grp)
774 volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
775 volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
777 mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
778 mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
781 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
782 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
785 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
786 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
789 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
790 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
791 mx6_grp_iomux->grp_addds = grp->grp_addds;
794 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
795 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
796 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
797 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
798 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
799 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
800 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
803 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
804 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
805 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
807 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
808 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
811 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
812 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
813 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
814 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
818 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
819 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
820 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
822 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
823 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
826 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
827 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
828 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
829 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
831 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
832 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
834 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
835 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
838 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
839 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
840 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
841 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
846 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
847 /* Configure MX6SDL mmdc iomux */
848 void mx6sdl_dram_iocfg(unsigned width,
849 const struct mx6sdl_iomux_ddr_regs *ddr,
850 const struct mx6sdl_iomux_grp_regs *grp)
852 volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
853 volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
855 mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
856 mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
859 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
860 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
863 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
864 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
867 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
868 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
869 mx6_grp_iomux->grp_addds = grp->grp_addds;
872 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
873 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
874 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
875 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
876 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
877 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
878 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
881 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
882 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
883 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
885 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
886 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
889 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
890 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
891 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
892 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
896 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
897 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
898 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
900 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
901 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
904 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
905 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
906 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
907 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
909 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
910 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
912 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
913 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
916 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
917 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
918 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
919 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
925 * Configure mx6 mmdc registers based on:
926 * - board-specific memory configuration
927 * - board-specific calibration data
928 * - ddr3/lpddr2 chip details
930 * The various calculations here are derived from the Freescale
931 * 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate
932 * MMDC configuration registers based on memory system and memory chip
935 * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
936 * configuration registers based on memory system and memory chip
939 * The defaults here are those which were specified in the spreadsheet.
940 * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
941 * and/or IMX6SLRM section titled MMDC initialization.
943 #define MR(val, ba, cmd, cs1) \
944 ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
945 #define MMDC1(entry, value) do { \
946 if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) \
947 mmdc1->entry = value; \
950 /* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */
951 #define BOOT_CFG3_DDR_MASK 0x30
952 #define BOOT_CFG3_EXT_DDR_MASK 0x33
954 #define DDR_MMAP_NOC_SINGLE 0
955 #define DDR_MMAP_NOC_DUAL 0x31
957 /* NoC ACTIVATE shifts */
958 #define NOC_RD_SHIFT 0
959 #define NOC_FAW_PERIOD_SHIFT 4
960 #define NOC_FAW_BANKS_SHIFT 10
962 /* NoC DdrTiming shifts */
963 #define NOC_ACT_TO_ACT_SHIFT 0
964 #define NOC_RD_TO_MISS_SHIFT 6
965 #define NOC_WR_TO_MISS_SHIFT 12
966 #define NOC_BURST_LEN_SHIFT 18
967 #define NOC_RD_TO_WR_SHIFT 21
968 #define NOC_WR_TO_RD_SHIFT 26
969 #define NOC_BW_RATIO_SHIFT 31
972 * According JESD209-2B-LPDDR2: Table 103
975 static int lpddr2_wl(uint32_t mem_speed)
990 puts("invalid memory speed\n");
998 * According JESD209-2B-LPDDR2: Table 103
1001 static int lpddr2_rl(uint32_t mem_speed)
1003 switch (mem_speed) {
1018 puts("invalid memory speed\n");
1025 void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
1026 const struct mx6_mmdc_calibration *calib,
1027 const struct mx6_lpddr2_cfg *lpddr2_cfg)
1029 volatile struct mmdc_p_regs *mmdc0;
1031 u8 tcke, tcksrx, tcksre, trrd;
1032 u8 twl, txp, tfaw, tcl;
1033 u16 tras, twr, tmrd, trtp, twtr, trfc, txsr;
1034 u16 trcd_lp, trppb_lp, trpab_lp, trc_lp;
1037 int clkper; /* clock period in picoseconds */
1038 int clock; /* clock freq in mHz */
1041 /* only support 16/32 bits */
1042 if (sysinfo->dsize > 1)
1045 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
1047 clock = mxc_get_clock(MXC_DDR_CLK) / 1000000U;
1048 clkper = (1000 * 1000) / clock; /* pico seconds */
1050 twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1;
1052 /* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */
1053 switch (lpddr2_cfg->density) {
1057 trfc = DIV_ROUND_UP(130000, clkper) - 1;
1058 txsr = DIV_ROUND_UP(140000, clkper) - 1;
1061 trfc = DIV_ROUND_UP(210000, clkper) - 1;
1062 txsr = DIV_ROUND_UP(220000, clkper) - 1;
1066 * 64Mb, 128Mb, 256Mb, 512Mb are not supported currently.
1072 * txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode,
1074 txp = DIV_ROUND_UP(7500, clkper) - 1;
1076 if (lpddr2_cfg->mem_speed == 333)
1077 tfaw = DIV_ROUND_UP(60000, clkper) - 1;
1079 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
1080 trrd = DIV_ROUND_UP(10000, clkper) - 1;
1082 /* tckesr for LPDDR2 */
1083 tcksre = DIV_ROUND_UP(15000, clkper);
1085 twr = DIV_ROUND_UP(15000, clkper) - 1;
1088 * tMRD should be set to max(tMRR, tMRW)
1091 tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1;
1092 /* LPDDR2 mode use tRCD_LP filed in MDCFG3. */
1093 trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1;
1094 trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp,
1096 trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1;
1097 trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1;
1098 /* To LPDDR2, CL in MDCFG0 refers to RL */
1099 tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3;
1100 twtr = DIV_ROUND_UP(7500, clkper) - 1;
1101 trtp = DIV_ROUND_UP(7500, clkper) - 1;
1103 cs0_end = 4 * sysinfo->cs_density - 1;
1105 debug("density:%d Gb (%d Gb per chip)\n",
1106 sysinfo->cs_density, lpddr2_cfg->density);
1107 debug("clock: %dMHz (%d ps)\n", clock, clkper);
1108 debug("memspd:%d\n", lpddr2_cfg->mem_speed);
1109 debug("trcd_lp=%d\n", trcd_lp);
1110 debug("trppb_lp=%d\n", trppb_lp);
1111 debug("trpab_lp=%d\n", trpab_lp);
1112 debug("trc_lp=%d\n", trc_lp);
1113 debug("tcke=%d\n", tcke);
1114 debug("tcksrx=%d\n", tcksrx);
1115 debug("tcksre=%d\n", tcksre);
1116 debug("trfc=%d\n", trfc);
1117 debug("txsr=%d\n", txsr);
1118 debug("txp=%d\n", txp);
1119 debug("tfaw=%d\n", tfaw);
1120 debug("tcl=%d\n", tcl);
1121 debug("tras=%d\n", tras);
1122 debug("twr=%d\n", twr);
1123 debug("tmrd=%d\n", tmrd);
1124 debug("twl=%d\n", twl);
1125 debug("trtp=%d\n", trtp);
1126 debug("twtr=%d\n", twtr);
1127 debug("trrd=%d\n", trrd);
1128 debug("cs0_end=%d\n", cs0_end);
1129 debug("ncs=%d\n", sysinfo->ncs);
1132 * board-specific configuration:
1133 * These values are determined empirically and vary per board layout
1135 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
1136 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
1137 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
1138 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
1139 mmdc0->mprddlctl = calib->p0_mprddlctl;
1140 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
1141 mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl;
1143 /* Read data DQ Byte0-3 delay */
1144 mmdc0->mprddqby0dl = 0x33333333;
1145 mmdc0->mprddqby1dl = 0x33333333;
1146 if (sysinfo->dsize > 0) {
1147 mmdc0->mprddqby2dl = 0x33333333;
1148 mmdc0->mprddqby3dl = 0x33333333;
1151 /* Write data DQ Byte0-3 delay */
1152 mmdc0->mpwrdqby0dl = 0xf3333333;
1153 mmdc0->mpwrdqby1dl = 0xf3333333;
1154 if (sysinfo->dsize > 0) {
1155 mmdc0->mpwrdqby2dl = 0xf3333333;
1156 mmdc0->mpwrdqby3dl = 0xf3333333;
1160 * In LPDDR2 mode this register should be cleared,
1161 * so no termination will be activated.
1163 mmdc0->mpodtctrl = 0;
1165 /* complete calibration */
1166 val = (1 << 11); /* Force measurement on delay-lines */
1167 mmdc0->mpmur0 = val;
1169 /* Step 1: configuration request */
1170 mmdc0->mdscr = (u32)(1 << 15); /* config request */
1172 /* Step 2: Timing configuration */
1173 mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) |
1175 mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl;
1176 mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;
1177 mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) |
1178 (trppb_lp << 4) | trpab_lp;
1181 mmdc0->mdasp = cs0_end; /* CS addressing */
1183 /* Step 3: Configure DDR type */
1184 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
1185 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
1186 (sysinfo->ralat << 6) | (1 << 3);
1188 /* Step 4: Configure delay while leaving reset */
1189 mmdc0->mdor = (sysinfo->sde_to_rst << 8) |
1190 (sysinfo->rst_to_cke << 0);
1192 /* Step 5: Configure DDR physical parameters (density and burst len) */
1193 coladdr = lpddr2_cfg->coladdr;
1194 if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
1196 else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
1198 mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */
1199 (coladdr - 9) << 20 | /* COL */
1200 (0 << 19) | /* Burst Length = 4 for LPDDR2 */
1201 (sysinfo->dsize << 16); /* DDR data bus size */
1203 /* Step 6: Perform ZQ calibration */
1204 val = 0xa1390003; /* one-time HW ZQ calib */
1205 mmdc0->mpzqhwctrl = val;
1207 /* Step 7: Enable MMDC with desired chip select */
1208 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
1209 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
1211 /* Step 8: Write Mode Registers to Init LPDDR2 devices */
1212 for (cs = 0; cs < sysinfo->ncs; cs++) {
1214 mmdc0->mdscr = MR(63, 0, 3, cs);
1215 /* MR10: calibration,
1216 * 0xff is calibration command after intilization.
1218 val = 0xA | (0xff << 8);
1219 mmdc0->mdscr = MR(val, 0, 3, cs);
1221 val = 0x1 | (0x82 << 8);
1222 mmdc0->mdscr = MR(val, 0, 3, cs);
1224 val = 0x2 | (0x04 << 8);
1225 mmdc0->mdscr = MR(val, 0, 3, cs);
1227 val = 0x3 | (0x02 << 8);
1228 mmdc0->mdscr = MR(val, 0, 3, cs);
1231 /* Step 10: Power down control and self-refresh */
1232 mmdc0->mdpdc = (tcke & 0x7) << 16 |
1233 5 << 12 | /* PWDT_1: 256 cycles */
1234 5 << 8 | /* PWDT_0: 256 cycles */
1235 1 << 6 | /* BOTH_CS_PD */
1236 (tcksrx & 0x7) << 3 |
1238 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
1240 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
1242 mmdc0->mpzqhwctrl = val;
1244 /* Step 12: Configure and activate periodic refresh */
1245 mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
1247 /* Step 13: Deassert config request - init complete */
1248 mmdc0->mdscr = 0x00000000;
1250 /* wait for auto-ZQ calibration to complete */
1254 void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
1255 const struct mx6_mmdc_calibration *calib,
1256 const struct mx6_ddr3_cfg *ddr3_cfg)
1258 volatile struct mmdc_p_regs *mmdc0;
1259 volatile struct mmdc_p_regs *mmdc1;
1260 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
1261 u8 soc_boot_cfg3 = (readl(&src_regs->sbmr1) >> 16) & 0xff;
1263 u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
1264 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
1265 u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
1266 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
1268 u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
1270 int clkper; /* clock period in picoseconds */
1271 int clock; /* clock freq in MHz */
1273 u16 mem_speed = ddr3_cfg->mem_speed;
1275 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
1276 if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
1277 mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
1279 /* Limit mem_speed for MX6D/MX6Q */
1280 if (is_mx6dq() || is_mx6dqp()) {
1281 if (mem_speed > 1066)
1282 mem_speed = 1066; /* 1066 MT/s */
1286 /* Limit mem_speed for MX6S/MX6DL */
1288 if (mem_speed > 800)
1289 mem_speed = 800; /* 800 MT/s */
1294 clock = mem_speed / 2;
1296 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
1297 * up to 528 MHz, so reduce the clock to fit chip specs
1299 if (is_mx6dq() || is_mx6dqp()) {
1301 clock = 528; /* 528 MHz */
1304 clkper = (1000 * 1000) / clock; /* pico seconds */
1309 switch (ddr3_cfg->density) {
1310 case 1: /* 1Gb per chip */
1311 trfc = DIV_ROUND_UP(110000, clkper) - 1;
1312 txs = DIV_ROUND_UP(120000, clkper) - 1;
1314 case 2: /* 2Gb per chip */
1315 trfc = DIV_ROUND_UP(160000, clkper) - 1;
1316 txs = DIV_ROUND_UP(170000, clkper) - 1;
1318 case 4: /* 4Gb per chip */
1319 trfc = DIV_ROUND_UP(260000, clkper) - 1;
1320 txs = DIV_ROUND_UP(270000, clkper) - 1;
1322 case 8: /* 8Gb per chip */
1323 trfc = DIV_ROUND_UP(350000, clkper) - 1;
1324 txs = DIV_ROUND_UP(360000, clkper) - 1;
1327 /* invalid density */
1328 puts("invalid chip density\n");
1334 switch (mem_speed) {
1336 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
1337 tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
1338 if (ddr3_cfg->pagesz == 1) {
1339 tfaw = DIV_ROUND_UP(40000, clkper) - 1;
1340 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
1342 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
1343 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
1347 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
1348 tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
1349 if (ddr3_cfg->pagesz == 1) {
1350 tfaw = DIV_ROUND_UP(37500, clkper) - 1;
1351 trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
1353 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
1354 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
1358 puts("invalid memory speed\n");
1362 txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
1363 tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
1364 taonpd = DIV_ROUND_UP(2000, clkper) - 1;
1367 twr = DIV_ROUND_UP(15000, clkper) - 1;
1368 tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
1369 trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
1370 tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
1371 tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
1372 trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
1373 twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
1376 cs0_end = 4 * sysinfo->cs_density - 1;
1378 debug("density:%d Gb (%d Gb per chip)\n",
1379 sysinfo->cs_density, ddr3_cfg->density);
1380 debug("clock: %dMHz (%d ps)\n", clock, clkper);
1381 debug("memspd:%d\n", mem_speed);
1382 debug("tcke=%d\n", tcke);
1383 debug("tcksrx=%d\n", tcksrx);
1384 debug("tcksre=%d\n", tcksre);
1385 debug("taofpd=%d\n", taofpd);
1386 debug("taonpd=%d\n", taonpd);
1387 debug("todtlon=%d\n", todtlon);
1388 debug("tanpd=%d\n", tanpd);
1389 debug("taxpd=%d\n", taxpd);
1390 debug("trfc=%d\n", trfc);
1391 debug("txs=%d\n", txs);
1392 debug("txp=%d\n", txp);
1393 debug("txpdll=%d\n", txpdll);
1394 debug("tfaw=%d\n", tfaw);
1395 debug("tcl=%d\n", tcl);
1396 debug("trcd=%d\n", trcd);
1397 debug("trp=%d\n", trp);
1398 debug("trc=%d\n", trc);
1399 debug("tras=%d\n", tras);
1400 debug("twr=%d\n", twr);
1401 debug("tmrd=%d\n", tmrd);
1402 debug("tcwl=%d\n", tcwl);
1403 debug("tdllk=%d\n", tdllk);
1404 debug("trtp=%d\n", trtp);
1405 debug("twtr=%d\n", twtr);
1406 debug("trrd=%d\n", trrd);
1407 debug("txpr=%d\n", txpr);
1408 debug("cs0_end=%d\n", cs0_end);
1409 debug("ncs=%d\n", sysinfo->ncs);
1410 debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
1411 debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
1412 debug("SRT=%d\n", ddr3_cfg->SRT);
1413 debug("twr=%d\n", twr);
1416 * board-specific configuration:
1417 * These values are determined empirically and vary per board layout
1419 * appnote, ddr3 spreadsheet
1421 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
1422 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
1423 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
1424 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
1425 mmdc0->mprddlctl = calib->p0_mprddlctl;
1426 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
1427 if (sysinfo->dsize > 1) {
1428 MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
1429 MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
1430 MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
1431 MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
1432 MMDC1(mprddlctl, calib->p1_mprddlctl);
1433 MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
1436 /* Read data DQ Byte0-3 delay */
1437 mmdc0->mprddqby0dl = 0x33333333;
1438 mmdc0->mprddqby1dl = 0x33333333;
1439 if (sysinfo->dsize > 0) {
1440 mmdc0->mprddqby2dl = 0x33333333;
1441 mmdc0->mprddqby3dl = 0x33333333;
1444 if (sysinfo->dsize > 1) {
1445 MMDC1(mprddqby0dl, 0x33333333);
1446 MMDC1(mprddqby1dl, 0x33333333);
1447 MMDC1(mprddqby2dl, 0x33333333);
1448 MMDC1(mprddqby3dl, 0x33333333);
1451 /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
1452 val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
1453 mmdc0->mpodtctrl = val;
1454 if (sysinfo->dsize > 1)
1455 MMDC1(mpodtctrl, val);
1457 /* complete calibration */
1458 val = (1 << 11); /* Force measurement on delay-lines */
1459 mmdc0->mpmur0 = val;
1460 if (sysinfo->dsize > 1)
1463 /* Step 1: configuration request */
1464 mmdc0->mdscr = (u32)(1 << 15); /* config request */
1466 /* Step 2: Timing configuration */
1467 mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
1468 (txpdll << 9) | (tfaw << 4) | tcl;
1469 mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
1470 (tras << 16) | (1 << 15) /* trpa */ |
1471 (twr << 9) | (tmrd << 5) | tcwl;
1472 mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
1473 mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
1474 (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
1475 mmdc0->mdasp = cs0_end; /* CS addressing */
1477 /* Step 3: Configure DDR type */
1478 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
1479 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
1480 (sysinfo->ralat << 6);
1482 /* Step 4: Configure delay while leaving reset */
1483 mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
1484 (sysinfo->rst_to_cke << 0);
1486 /* Step 5: Configure DDR physical parameters (density and burst len) */
1487 coladdr = ddr3_cfg->coladdr;
1488 if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
1490 else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
1492 mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
1493 (coladdr - 9) << 20 | /* COL */
1494 (1 << 19) | /* Burst Length = 8 for DDR3 */
1495 (sysinfo->dsize << 16); /* DDR data bus size */
1497 /* Step 6: Perform ZQ calibration */
1498 val = 0xa1390001; /* one-time HW ZQ calib */
1499 mmdc0->mpzqhwctrl = val;
1500 if (sysinfo->dsize > 1)
1501 MMDC1(mpzqhwctrl, val);
1503 /* Step 7: Enable MMDC with desired chip select */
1504 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
1505 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
1507 /* Step 8: Write Mode Registers to Init DDR3 devices */
1508 for (cs = 0; cs < sysinfo->ncs; cs++) {
1510 val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
1511 ((tcwl - 3) & 3) << 3;
1512 debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
1513 mmdc0->mdscr = MR(val, 2, 3, cs);
1515 debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
1516 mmdc0->mdscr = MR(0, 3, 3, cs);
1518 val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
1519 ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
1520 debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
1521 mmdc0->mdscr = MR(val, 1, 3, cs);
1523 val = ((tcl - 1) << 4) | /* CAS */
1524 (1 << 8) | /* DLL Reset */
1525 ((twr - 3) << 9) | /* Write Recovery */
1526 (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
1527 debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
1528 mmdc0->mdscr = MR(val, 0, 3, cs);
1529 /* ZQ calibration */
1531 mmdc0->mdscr = MR(val, 0, 4, cs);
1534 /* Step 10: Power down control and self-refresh */
1535 mmdc0->mdpdc = (tcke & 0x7) << 16 |
1536 5 << 12 | /* PWDT_1: 256 cycles */
1537 5 << 8 | /* PWDT_0: 256 cycles */
1538 1 << 6 | /* BOTH_CS_PD */
1539 (tcksrx & 0x7) << 3 |
1541 if (!sysinfo->pd_fast_exit)
1542 mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
1543 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
1545 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
1547 mmdc0->mpzqhwctrl = val;
1548 if (sysinfo->dsize > 1)
1549 MMDC1(mpzqhwctrl, val);
1551 /* Step 12: Configure and activate periodic refresh */
1552 mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
1555 * Step 13: i.MX6DQP only: If the NoC scheduler is enabled,
1556 * configure it and disable MMDC arbitration/reordering (see EB828)
1559 ((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE ||
1560 (soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) {
1561 struct mx6dqp_noc_sched_regs *noc_sched =
1562 (struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE;
1565 * These values are fixed based on integration parameters and
1566 * should not be modified
1568 noc_sched->rlat = 0x00000040;
1569 noc_sched->ipu1 = 0x00000020;
1570 noc_sched->ipu2 = 0x00000020;
1572 noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) |
1573 (tfaw << NOC_FAW_PERIOD_SHIFT) |
1574 (trrd << NOC_RD_SHIFT);
1575 noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0)
1576 << NOC_BW_RATIO_SHIFT) |
1577 ((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) |
1578 ((tcl - tcwl + 2) << NOC_RD_TO_WR_SHIFT) |
1579 (4 << NOC_BURST_LEN_SHIFT) | /* BL8 */
1580 ((tcwl + twr + trp + trcd)
1581 << NOC_WR_TO_MISS_SHIFT) |
1582 ((trtp + trp + trcd - 4)
1583 << NOC_RD_TO_MISS_SHIFT) |
1584 (trc << NOC_ACT_TO_ACT_SHIFT);
1586 if (sysinfo->dsize == 2) {
1587 if (ddr3_cfg->coladdr == 10) {
1588 if (ddr3_cfg->rowaddr == 15 &&
1590 noc_sched->ddrconf = 4;
1592 noc_sched->ddrconf = 0;
1593 } else if (ddr3_cfg->coladdr == 11) {
1594 noc_sched->ddrconf = 1;
1597 if (ddr3_cfg->coladdr == 9) {
1598 if (ddr3_cfg->rowaddr == 13)
1599 noc_sched->ddrconf = 2;
1600 else if (ddr3_cfg->rowaddr == 14)
1601 noc_sched->ddrconf = 15;
1602 } else if (ddr3_cfg->coladdr == 10) {
1603 if (ddr3_cfg->rowaddr == 14 &&
1605 noc_sched->ddrconf = 14;
1606 else if (ddr3_cfg->rowaddr == 15 &&
1608 noc_sched->ddrconf = 9;
1610 noc_sched->ddrconf = 3;
1611 } else if (ddr3_cfg->coladdr == 11) {
1612 if (ddr3_cfg->rowaddr == 15 &&
1614 noc_sched->ddrconf = 4;
1616 noc_sched->ddrconf = 0;
1617 } else if (ddr3_cfg->coladdr == 12) {
1618 if (ddr3_cfg->rowaddr == 14)
1619 noc_sched->ddrconf = 1;
1623 /* Disable MMDC arbitration/reordering */
1624 mmdc0->maarcr = 0x14420000;
1627 /* Step 13: Deassert config request - init complete */
1628 mmdc0->mdscr = 0x00000000;
1630 /* wait for auto-ZQ calibration to complete */
1634 void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
1635 struct mx6_mmdc_calibration *calib)
1637 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
1638 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
1640 calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0);
1641 calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1);
1642 calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0);
1643 calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1);
1644 calib->p0_mprddlctl = readl(&mmdc0->mprddlctl);
1645 calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl);
1647 if (sysinfo->dsize == 2) {
1648 calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0);
1649 calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1);
1650 calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0);
1651 calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1);
1652 calib->p1_mprddlctl = readl(&mmdc1->mprddlctl);
1653 calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl);
1657 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
1658 const struct mx6_mmdc_calibration *calib,
1659 const void *ddr_cfg)
1661 if (sysinfo->ddr_type == DDR_TYPE_DDR3) {
1662 mx6_ddr3_cfg(sysinfo, calib, ddr_cfg);
1663 } else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) {
1664 mx6_lpddr2_cfg(sysinfo, calib, ddr_cfg);
1666 puts("Unsupported ddr type\n");