1 // SPDX-License-Identifier: GPL-2.0+
4 * Sascha Hauer, Pengutronix
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
13 #include <linux/errno.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/crm_regs.h>
16 #include <asm/arch/clock.h>
18 #include <asm/arch/sys_proto.h>
30 struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
31 [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
32 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
33 [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
35 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
39 #define AHB_CLK_ROOT 133333333
40 #define SZ_DEC_1M 1000000
41 #define PLL_PD_MAX 16 /* Actual pd+1 */
42 #define PLL_MFI_MAX 15
50 #define MX5_CBCMR 0x00015154
51 #define MX5_CBCDR 0x02888945
53 struct fixed_pll_mfd {
58 const struct fixed_pll_mfd fixed_mfd[] = {
69 #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
70 #define PLL_FREQ_MIN(ref_clk) \
71 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
72 #define MAX_DDR_CLK 420000000
73 #define NFC_CLK_MAX 34000000
75 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
77 void set_usboh3_clk(void)
79 clrsetbits_le32(&mxc_ccm->cscmr1,
80 MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
81 MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
82 clrsetbits_le32(&mxc_ccm->cscdr1,
83 MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
84 MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
85 MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
86 MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
89 void enable_usboh3_clk(bool enable)
91 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
93 clrsetbits_le32(&mxc_ccm->CCGR2,
94 MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
95 MXC_CCM_CCGR2_USBOH3_60M(cg));
98 #ifdef CONFIG_SYS_I2C_MXC
99 /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
100 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
104 #if defined(CONFIG_MX51)
106 #elif defined(CONFIG_MX53)
110 mask = MXC_CCM_CCGR_CG_MASK <<
111 (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
113 setbits_le32(&mxc_ccm->CCGR1, mask);
115 clrbits_le32(&mxc_ccm->CCGR1, mask);
120 void set_usb_phy_clk(void)
122 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
125 #if defined(CONFIG_MX51)
126 void enable_usb_phy1_clk(bool enable)
128 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
130 clrsetbits_le32(&mxc_ccm->CCGR2,
131 MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
132 MXC_CCM_CCGR2_USB_PHY(cg));
135 void enable_usb_phy2_clk(bool enable)
137 /* i.MX51 has a single USB PHY clock, so do nothing here. */
139 #elif defined(CONFIG_MX53)
140 void enable_usb_phy1_clk(bool enable)
142 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
144 clrsetbits_le32(&mxc_ccm->CCGR4,
145 MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
146 MXC_CCM_CCGR4_USB_PHY1(cg));
149 void enable_usb_phy2_clk(bool enable)
151 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
153 clrsetbits_le32(&mxc_ccm->CCGR4,
154 MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
155 MXC_CCM_CCGR4_USB_PHY2(cg));
160 * Calculate the frequency of PLLn.
162 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
164 uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
165 uint64_t refclk, temp;
168 ctrl = readl(&pll->ctrl);
170 if (ctrl & MXC_DPLLC_CTL_HFSM) {
171 mfn = readl(&pll->hfs_mfn);
172 mfd = readl(&pll->hfs_mfd);
173 op = readl(&pll->hfs_op);
175 mfn = readl(&pll->mfn);
176 mfd = readl(&pll->mfd);
177 op = readl(&pll->op);
180 mfd &= MXC_DPLLC_MFD_MFD_MASK;
181 mfn &= MXC_DPLLC_MFN_MFN_MASK;
182 pdf = op & MXC_DPLLC_OP_PDF_MASK;
183 mfi = MXC_DPLLC_OP_MFI_RD(op);
190 if (mfn >= 0x04000000) {
197 if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
200 do_div(refclk, pdf + 1);
201 temp = refclk * mfn_abs;
202 do_div(temp, mfd + 1);
215 * This function returns the Frequency Pre-Multiplier clock.
217 static u32 get_fpm(void)
220 u32 ccr = readl(&mxc_ccm->ccr);
222 if (ccr & MXC_CCM_CCR_FPM_MULT)
227 return MXC_CLK32 * mult;
232 * This function returns the low power audio clock.
234 static u32 get_lp_apm(void)
237 u32 ccsr = readl(&mxc_ccm->ccsr);
239 if (ccsr & MXC_CCM_CCSR_LP_APM)
240 #if defined(CONFIG_MX51)
242 #elif defined(CONFIG_MX53)
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
254 u32 get_mcu_main_clk(void)
258 reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
260 return freq / (reg + 1);
264 * Get the rate of peripheral's root clock.
266 u32 get_periph_clk(void)
270 reg = readl(&mxc_ccm->cbcdr);
271 if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
273 reg = readl(&mxc_ccm->cbcmr);
274 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
288 * Get the rate of ipg clock.
290 static u32 get_ipg_clk(void)
292 uint32_t freq, reg, div;
294 freq = get_ahb_clk();
296 reg = readl(&mxc_ccm->cbcdr);
297 div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
303 * Get the rate of ipg_per clock.
305 static u32 get_ipg_per_clk(void)
307 u32 freq, pred1, pred2, podf;
309 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
310 return get_ipg_clk();
312 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
315 freq = get_periph_clk();
316 podf = readl(&mxc_ccm->cbcdr);
317 pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
318 pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
319 podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
320 return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
323 /* Get the output clock rate of a standard PLL MUX for peripherals. */
324 static u32 get_standard_pll_sel_clk(u32 clk_sel)
328 switch (clk_sel & 0x3) {
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
347 * Get the rate of uart clk.
349 static u32 get_uart_clk(void)
351 unsigned int clk_sel, freq, reg, pred, podf;
353 reg = readl(&mxc_ccm->cscmr1);
354 clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
355 freq = get_standard_pll_sel_clk(clk_sel);
357 reg = readl(&mxc_ccm->cscdr1);
358 pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
359 podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
360 freq /= (pred + 1) * (podf + 1);
366 * get cspi clock rate.
368 static u32 imx_get_cspiclk(void)
370 u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
371 u32 cscmr1 = readl(&mxc_ccm->cscmr1);
372 u32 cscdr2 = readl(&mxc_ccm->cscdr2);
374 pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
375 pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
376 clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
377 freq = get_standard_pll_sel_clk(clk_sel);
378 ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
383 * get esdhc clock rate.
385 static u32 get_esdhc_clk(u32 port)
387 u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
388 u32 cscmr1 = readl(&mxc_ccm->cscmr1);
389 u32 cscdr1 = readl(&mxc_ccm->cscdr1);
393 clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
394 pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
395 podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
398 clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
399 pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
400 podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
403 if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
404 return get_esdhc_clk(1);
406 return get_esdhc_clk(0);
408 if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
409 return get_esdhc_clk(1);
411 return get_esdhc_clk(0);
416 freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
420 static u32 get_axi_a_clk(void)
422 u32 cbcdr = readl(&mxc_ccm->cbcdr);
423 u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
425 return get_periph_clk() / (pdf + 1);
428 static u32 get_axi_b_clk(void)
430 u32 cbcdr = readl(&mxc_ccm->cbcdr);
431 u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
433 return get_periph_clk() / (pdf + 1);
436 static u32 get_emi_slow_clk(void)
438 u32 cbcdr = readl(&mxc_ccm->cbcdr);
439 u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
440 u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
443 return get_ahb_clk() / (pdf + 1);
445 return get_periph_clk() / (pdf + 1);
448 static u32 get_ddr_clk(void)
451 u32 cbcmr = readl(&mxc_ccm->cbcmr);
452 u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
454 u32 cbcdr = readl(&mxc_ccm->cbcdr);
455 if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
456 u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
458 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
459 ret_val /= ddr_clk_podf + 1;
464 switch (ddr_clk_sel) {
466 ret_val = get_axi_a_clk();
469 ret_val = get_axi_b_clk();
472 ret_val = get_emi_slow_clk();
475 ret_val = get_ahb_clk();
485 * The API of get mxc clocks.
487 unsigned int mxc_get_clock(enum mxc_clock clk)
491 return get_mcu_main_clk();
493 return get_ahb_clk();
495 return get_ipg_clk();
498 return get_ipg_per_clk();
500 return get_uart_clk();
502 return imx_get_cspiclk();
504 return get_esdhc_clk(0);
506 return get_esdhc_clk(1);
508 return get_esdhc_clk(2);
510 return get_esdhc_clk(3);
512 return get_ipg_clk();
514 return get_ahb_clk();
516 return get_ddr_clk();
523 u32 imx_get_uartclk(void)
525 return get_uart_clk();
528 u32 imx_get_fecclk(void)
530 return get_ipg_clk();
533 static int gcd(int m, int n)
548 * This is to calculate various parameters based on reference clock and
549 * targeted clock based on the equation:
550 * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
551 * This calculation is based on a fixed MFD value for simplicity.
553 static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
555 u64 pd, mfi = 1, mfn, mfd, t1;
556 u32 n_target = target;
560 * Make sure targeted freq is in the valid range.
561 * Otherwise the following calculation might be wrong!!!
563 if (n_target < PLL_FREQ_MIN(ref) ||
564 n_target > PLL_FREQ_MAX(ref)) {
565 printf("Targeted peripheral clock should be"
566 "within [%d - %d]\n",
567 PLL_FREQ_MIN(ref) / SZ_DEC_1M,
568 PLL_FREQ_MAX(ref) / SZ_DEC_1M);
572 for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
573 if (fixed_mfd[i].ref_clk_hz == ref) {
574 mfd = fixed_mfd[i].mfd;
579 if (i == ARRAY_SIZE(fixed_mfd))
582 /* Use n_target and n_ref to avoid overflow */
583 for (pd = 1; pd <= PLL_PD_MAX; pd++) {
585 do_div(t1, (4 * n_ref));
587 if (mfi > PLL_MFI_MAX)
594 * Now got pd and mfi already
596 * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
604 debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
605 ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
619 #define calc_div(tgt_clk, src_clk, limit) ({ \
621 if (((src_clk) % (tgt_clk)) <= 100) \
622 v = (src_clk) / (tgt_clk); \
624 v = ((src_clk) / (tgt_clk)) + 1;\
630 #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
632 writel(0x1232, &pll->ctrl); \
633 writel(0x2, &pll->config); \
634 writel((((pd) - 1) << 0) | ((fi) << 4), \
636 writel(fn, &(pll->mfn)); \
637 writel((fd) - 1, &pll->mfd); \
638 writel((((pd) - 1) << 0) | ((fi) << 4), \
640 writel(fn, &pll->hfs_mfn); \
641 writel((fd) - 1, &pll->hfs_mfd); \
642 writel(0x1232, &pll->ctrl); \
643 while (!readl(&pll->ctrl) & 0x1) \
647 static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
649 u32 ccsr = readl(&mxc_ccm->ccsr);
650 struct mxc_pll_reg *pll = mxc_plls[index];
654 /* Switch ARM to PLL2 clock */
655 writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
657 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
658 pll_param->mfi, pll_param->mfn,
661 writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
665 /* Switch to pll2 bypass clock */
666 writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
668 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
669 pll_param->mfi, pll_param->mfn,
672 writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
676 /* Switch to pll3 bypass clock */
677 writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
679 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
680 pll_param->mfi, pll_param->mfn,
683 writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
688 /* Switch to pll4 bypass clock */
689 writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
691 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
692 pll_param->mfi, pll_param->mfn,
695 writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
706 /* Config CPU clock */
707 static int config_core_clk(u32 ref, u32 freq)
710 struct pll_param pll_param;
712 memset(&pll_param, 0, sizeof(struct pll_param));
714 /* The case that periph uses PLL1 is not considered here */
715 ret = calc_pll_params(ref, freq, &pll_param);
717 printf("Error:Can't find pll parameters: %d\n", ret);
721 return config_pll_clk(PLL1_CLOCK, &pll_param);
724 static int config_nfc_clk(u32 nfc_clk)
726 u32 parent_rate = get_emi_slow_clk();
731 div = parent_rate / nfc_clk;
734 if (parent_rate / div > NFC_CLK_MAX)
736 clrsetbits_le32(&mxc_ccm->cbcdr,
737 MXC_CCM_CBCDR_NFC_PODF_MASK,
738 MXC_CCM_CBCDR_NFC_PODF(div - 1));
739 while (readl(&mxc_ccm->cdhipr) != 0)
744 void enable_nfc_clk(unsigned char enable)
746 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
748 clrsetbits_le32(&mxc_ccm->CCGR5,
749 MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
750 MXC_CCM_CCGR5_EMI_ENFC(cg));
753 #ifdef CONFIG_FSL_IIM
754 void enable_efuse_prog_supply(bool enable)
757 setbits_le32(&mxc_ccm->cgpr,
758 MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
760 clrbits_le32(&mxc_ccm->cgpr,
761 MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
765 /* Config main_bus_clock for periphs */
766 static int config_periph_clk(u32 ref, u32 freq)
769 struct pll_param pll_param;
771 memset(&pll_param, 0, sizeof(struct pll_param));
773 if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
774 ret = calc_pll_params(ref, freq, &pll_param);
776 printf("Error:Can't find pll parameters: %d\n",
780 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
781 readl(&mxc_ccm->cbcmr))) {
783 return config_pll_clk(PLL1_CLOCK, &pll_param);
786 return config_pll_clk(PLL3_CLOCK, &pll_param);
796 static int config_ddr_clk(u32 emi_clk)
799 s32 shift = 0, clk_sel, div = 1;
800 u32 cbcmr = readl(&mxc_ccm->cbcmr);
802 if (emi_clk > MAX_DDR_CLK) {
803 printf("Warning:DDR clock should not exceed %d MHz\n",
804 MAX_DDR_CLK / SZ_DEC_1M);
805 emi_clk = MAX_DDR_CLK;
808 clk_src = get_periph_clk();
809 /* Find DDR clock input */
810 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
828 if ((clk_src % emi_clk) < 10000000)
829 div = clk_src / emi_clk;
831 div = (clk_src / emi_clk) + 1;
835 clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
836 while (readl(&mxc_ccm->cdhipr) != 0)
838 writel(0x0, &mxc_ccm->ccdr);
844 static int config_ldb_clk(u32 ref, u32 freq)
847 struct pll_param pll_param;
849 memset(&pll_param, 0, sizeof(struct pll_param));
851 ret = calc_pll_params(ref, freq, &pll_param);
853 printf("Error:Can't find pll parameters: %d\n",
858 return config_pll_clk(PLL4_CLOCK, &pll_param);
861 static int config_ldb_clk(u32 ref, u32 freq)
863 /* Platform not supported */
869 * This function assumes the expected core clock has to be changed by
870 * modifying the PLL. This is NOT true always but for most of the times,
871 * it is. So it assumes the PLL output freq is the same as the expected
872 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
873 * In the latter case, it will try to increase the presc value until
874 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
875 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
876 * on the targeted PLL and reference input clock to the PLL. Lastly,
877 * it sets the register based on these values along with the dividers.
878 * Note 1) There is no value checking for the passed-in divider values
879 * so the caller has to make sure those values are sensible.
880 * 2) Also adjust the NFC divider such that the NFC clock doesn't
881 * exceed NFC_CLK_MAX.
882 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
883 * 177MHz for higher voltage, this function fixes the max to 133MHz.
884 * 4) This function should not have allowed diag_printf() calls since
885 * the serial driver has been stoped. But leave then here to allow
886 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
888 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
894 if (config_core_clk(ref, freq))
898 if (config_periph_clk(ref, freq))
902 if (config_ddr_clk(freq))
906 if (config_nfc_clk(freq))
910 if (config_ldb_clk(ref, freq))
914 printf("Warning:Unsupported or invalid clock type\n");
922 * The clock for the external interface can be set to use internal clock
923 * if fuse bank 4, row 3, bit 2 is set.
924 * This is an undocumented feature and it was confirmed by Freescale's support:
925 * Fuses (but not pins) may be used to configure SATA clocks.
926 * Particularly the i.MX53 Fuse_Map contains the next information
927 * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
928 * '00' - 100MHz (External)
929 * '01' - 50MHz (External)
930 * '10' - 120MHz, internal (USB PHY)
933 void mxc_set_sata_internal_clock(void)
936 (u32 *)(IIM_BASE_ADDR + 0x180c);
940 clrsetbits_le32(tmp_base, 0x6, 0x4);
944 #ifndef CONFIG_SPL_BUILD
946 * Dump some core clockes.
948 static int do_mx5_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
954 printf("PLL1 %8d MHz\n", freq / 1000000);
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
956 printf("PLL2 %8d MHz\n", freq / 1000000);
957 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
958 printf("PLL3 %8d MHz\n", freq / 1000000);
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
961 printf("PLL4 %8d MHz\n", freq / 1000000);
965 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
966 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
967 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
968 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
969 #ifdef CONFIG_MXC_SPI
970 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
975 /***************************************************/
978 clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,