1 // SPDX-License-Identifier: GPL-2.0+
4 * Sascha Hauer, Pengutronix
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
11 #include <linux/errno.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
28 struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
29 [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
30 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
31 [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
33 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
37 #define AHB_CLK_ROOT 133333333
38 #define SZ_DEC_1M 1000000
39 #define PLL_PD_MAX 16 /* Actual pd+1 */
40 #define PLL_MFI_MAX 15
48 #define MX5_CBCMR 0x00015154
49 #define MX5_CBCDR 0x02888945
51 struct fixed_pll_mfd {
56 const struct fixed_pll_mfd fixed_mfd[] = {
67 #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
68 #define PLL_FREQ_MIN(ref_clk) \
69 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
70 #define MAX_DDR_CLK 420000000
71 #define NFC_CLK_MAX 34000000
73 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
75 void set_usboh3_clk(void)
77 clrsetbits_le32(&mxc_ccm->cscmr1,
78 MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
79 MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
80 clrsetbits_le32(&mxc_ccm->cscdr1,
81 MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
82 MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
83 MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
84 MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
87 void enable_usboh3_clk(bool enable)
89 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
91 clrsetbits_le32(&mxc_ccm->CCGR2,
92 MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
93 MXC_CCM_CCGR2_USBOH3_60M(cg));
96 #ifdef CONFIG_SYS_I2C_MXC
97 /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
98 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
102 #if defined(CONFIG_MX51)
104 #elif defined(CONFIG_MX53)
108 mask = MXC_CCM_CCGR_CG_MASK <<
109 (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
111 setbits_le32(&mxc_ccm->CCGR1, mask);
113 clrbits_le32(&mxc_ccm->CCGR1, mask);
118 void set_usb_phy_clk(void)
120 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
123 #if defined(CONFIG_MX51)
124 void enable_usb_phy1_clk(bool enable)
126 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
128 clrsetbits_le32(&mxc_ccm->CCGR2,
129 MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
130 MXC_CCM_CCGR2_USB_PHY(cg));
133 void enable_usb_phy2_clk(bool enable)
135 /* i.MX51 has a single USB PHY clock, so do nothing here. */
137 #elif defined(CONFIG_MX53)
138 void enable_usb_phy1_clk(bool enable)
140 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
142 clrsetbits_le32(&mxc_ccm->CCGR4,
143 MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
144 MXC_CCM_CCGR4_USB_PHY1(cg));
147 void enable_usb_phy2_clk(bool enable)
149 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
151 clrsetbits_le32(&mxc_ccm->CCGR4,
152 MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
153 MXC_CCM_CCGR4_USB_PHY2(cg));
158 * Calculate the frequency of PLLn.
160 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
162 uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
163 uint64_t refclk, temp;
166 ctrl = readl(&pll->ctrl);
168 if (ctrl & MXC_DPLLC_CTL_HFSM) {
169 mfn = readl(&pll->hfs_mfn);
170 mfd = readl(&pll->hfs_mfd);
171 op = readl(&pll->hfs_op);
173 mfn = readl(&pll->mfn);
174 mfd = readl(&pll->mfd);
175 op = readl(&pll->op);
178 mfd &= MXC_DPLLC_MFD_MFD_MASK;
179 mfn &= MXC_DPLLC_MFN_MFN_MASK;
180 pdf = op & MXC_DPLLC_OP_PDF_MASK;
181 mfi = MXC_DPLLC_OP_MFI_RD(op);
188 if (mfn >= 0x04000000) {
195 if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
198 do_div(refclk, pdf + 1);
199 temp = refclk * mfn_abs;
200 do_div(temp, mfd + 1);
213 * This function returns the Frequency Pre-Multiplier clock.
215 static u32 get_fpm(void)
218 u32 ccr = readl(&mxc_ccm->ccr);
220 if (ccr & MXC_CCM_CCR_FPM_MULT)
225 return MXC_CLK32 * mult;
230 * This function returns the low power audio clock.
232 static u32 get_lp_apm(void)
235 u32 ccsr = readl(&mxc_ccm->ccsr);
237 if (ccsr & MXC_CCM_CCSR_LP_APM)
238 #if defined(CONFIG_MX51)
240 #elif defined(CONFIG_MX53)
241 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
252 u32 get_mcu_main_clk(void)
256 reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
257 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
258 return freq / (reg + 1);
262 * Get the rate of peripheral's root clock.
264 u32 get_periph_clk(void)
268 reg = readl(&mxc_ccm->cbcdr);
269 if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
270 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
271 reg = readl(&mxc_ccm->cbcmr);
272 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
274 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
276 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
286 * Get the rate of ipg clock.
288 static u32 get_ipg_clk(void)
290 uint32_t freq, reg, div;
292 freq = get_ahb_clk();
294 reg = readl(&mxc_ccm->cbcdr);
295 div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
301 * Get the rate of ipg_per clock.
303 static u32 get_ipg_per_clk(void)
305 u32 freq, pred1, pred2, podf;
307 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
308 return get_ipg_clk();
310 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
313 freq = get_periph_clk();
314 podf = readl(&mxc_ccm->cbcdr);
315 pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
316 pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
317 podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
318 return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
321 /* Get the output clock rate of a standard PLL MUX for peripherals. */
322 static u32 get_standard_pll_sel_clk(u32 clk_sel)
326 switch (clk_sel & 0x3) {
328 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
331 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
334 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
345 * Get the rate of uart clk.
347 static u32 get_uart_clk(void)
349 unsigned int clk_sel, freq, reg, pred, podf;
351 reg = readl(&mxc_ccm->cscmr1);
352 clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
353 freq = get_standard_pll_sel_clk(clk_sel);
355 reg = readl(&mxc_ccm->cscdr1);
356 pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
357 podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
358 freq /= (pred + 1) * (podf + 1);
364 * get cspi clock rate.
366 static u32 imx_get_cspiclk(void)
368 u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
369 u32 cscmr1 = readl(&mxc_ccm->cscmr1);
370 u32 cscdr2 = readl(&mxc_ccm->cscdr2);
372 pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
373 pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
374 clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
375 freq = get_standard_pll_sel_clk(clk_sel);
376 ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
381 * get esdhc clock rate.
383 static u32 get_esdhc_clk(u32 port)
385 u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
386 u32 cscmr1 = readl(&mxc_ccm->cscmr1);
387 u32 cscdr1 = readl(&mxc_ccm->cscdr1);
391 clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
392 pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
393 podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
396 clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
397 pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
398 podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
401 if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
402 return get_esdhc_clk(1);
404 return get_esdhc_clk(0);
406 if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
407 return get_esdhc_clk(1);
409 return get_esdhc_clk(0);
414 freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
418 static u32 get_axi_a_clk(void)
420 u32 cbcdr = readl(&mxc_ccm->cbcdr);
421 u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
423 return get_periph_clk() / (pdf + 1);
426 static u32 get_axi_b_clk(void)
428 u32 cbcdr = readl(&mxc_ccm->cbcdr);
429 u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
431 return get_periph_clk() / (pdf + 1);
434 static u32 get_emi_slow_clk(void)
436 u32 cbcdr = readl(&mxc_ccm->cbcdr);
437 u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
438 u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
441 return get_ahb_clk() / (pdf + 1);
443 return get_periph_clk() / (pdf + 1);
446 static u32 get_ddr_clk(void)
449 u32 cbcmr = readl(&mxc_ccm->cbcmr);
450 u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
452 u32 cbcdr = readl(&mxc_ccm->cbcdr);
453 if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
454 u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
456 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
457 ret_val /= ddr_clk_podf + 1;
462 switch (ddr_clk_sel) {
464 ret_val = get_axi_a_clk();
467 ret_val = get_axi_b_clk();
470 ret_val = get_emi_slow_clk();
473 ret_val = get_ahb_clk();
483 * The API of get mxc clocks.
485 unsigned int mxc_get_clock(enum mxc_clock clk)
489 return get_mcu_main_clk();
491 return get_ahb_clk();
493 return get_ipg_clk();
496 return get_ipg_per_clk();
498 return get_uart_clk();
500 return imx_get_cspiclk();
502 return get_esdhc_clk(0);
504 return get_esdhc_clk(1);
506 return get_esdhc_clk(2);
508 return get_esdhc_clk(3);
510 return get_ipg_clk();
512 return get_ahb_clk();
514 return get_ddr_clk();
521 u32 imx_get_uartclk(void)
523 return get_uart_clk();
526 u32 imx_get_fecclk(void)
528 return get_ipg_clk();
531 static int gcd(int m, int n)
546 * This is to calculate various parameters based on reference clock and
547 * targeted clock based on the equation:
548 * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
549 * This calculation is based on a fixed MFD value for simplicity.
551 static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
553 u64 pd, mfi = 1, mfn, mfd, t1;
554 u32 n_target = target;
558 * Make sure targeted freq is in the valid range.
559 * Otherwise the following calculation might be wrong!!!
561 if (n_target < PLL_FREQ_MIN(ref) ||
562 n_target > PLL_FREQ_MAX(ref)) {
563 printf("Targeted peripheral clock should be"
564 "within [%d - %d]\n",
565 PLL_FREQ_MIN(ref) / SZ_DEC_1M,
566 PLL_FREQ_MAX(ref) / SZ_DEC_1M);
570 for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
571 if (fixed_mfd[i].ref_clk_hz == ref) {
572 mfd = fixed_mfd[i].mfd;
577 if (i == ARRAY_SIZE(fixed_mfd))
580 /* Use n_target and n_ref to avoid overflow */
581 for (pd = 1; pd <= PLL_PD_MAX; pd++) {
583 do_div(t1, (4 * n_ref));
585 if (mfi > PLL_MFI_MAX)
592 * Now got pd and mfi already
594 * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
602 debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
603 ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
617 #define calc_div(tgt_clk, src_clk, limit) ({ \
619 if (((src_clk) % (tgt_clk)) <= 100) \
620 v = (src_clk) / (tgt_clk); \
622 v = ((src_clk) / (tgt_clk)) + 1;\
628 #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
630 writel(0x1232, &pll->ctrl); \
631 writel(0x2, &pll->config); \
632 writel((((pd) - 1) << 0) | ((fi) << 4), \
634 writel(fn, &(pll->mfn)); \
635 writel((fd) - 1, &pll->mfd); \
636 writel((((pd) - 1) << 0) | ((fi) << 4), \
638 writel(fn, &pll->hfs_mfn); \
639 writel((fd) - 1, &pll->hfs_mfd); \
640 writel(0x1232, &pll->ctrl); \
641 while (!readl(&pll->ctrl) & 0x1) \
645 static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
647 u32 ccsr = readl(&mxc_ccm->ccsr);
648 struct mxc_pll_reg *pll = mxc_plls[index];
652 /* Switch ARM to PLL2 clock */
653 writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
655 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
656 pll_param->mfi, pll_param->mfn,
659 writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
663 /* Switch to pll2 bypass clock */
664 writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
666 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
667 pll_param->mfi, pll_param->mfn,
670 writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
674 /* Switch to pll3 bypass clock */
675 writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
677 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
678 pll_param->mfi, pll_param->mfn,
681 writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
686 /* Switch to pll4 bypass clock */
687 writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
689 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
690 pll_param->mfi, pll_param->mfn,
693 writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
704 /* Config CPU clock */
705 static int config_core_clk(u32 ref, u32 freq)
708 struct pll_param pll_param;
710 memset(&pll_param, 0, sizeof(struct pll_param));
712 /* The case that periph uses PLL1 is not considered here */
713 ret = calc_pll_params(ref, freq, &pll_param);
715 printf("Error:Can't find pll parameters: %d\n", ret);
719 return config_pll_clk(PLL1_CLOCK, &pll_param);
722 static int config_nfc_clk(u32 nfc_clk)
724 u32 parent_rate = get_emi_slow_clk();
729 div = parent_rate / nfc_clk;
732 if (parent_rate / div > NFC_CLK_MAX)
734 clrsetbits_le32(&mxc_ccm->cbcdr,
735 MXC_CCM_CBCDR_NFC_PODF_MASK,
736 MXC_CCM_CBCDR_NFC_PODF(div - 1));
737 while (readl(&mxc_ccm->cdhipr) != 0)
742 void enable_nfc_clk(unsigned char enable)
744 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
746 clrsetbits_le32(&mxc_ccm->CCGR5,
747 MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
748 MXC_CCM_CCGR5_EMI_ENFC(cg));
751 #ifdef CONFIG_FSL_IIM
752 void enable_efuse_prog_supply(bool enable)
755 setbits_le32(&mxc_ccm->cgpr,
756 MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
758 clrbits_le32(&mxc_ccm->cgpr,
759 MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
763 /* Config main_bus_clock for periphs */
764 static int config_periph_clk(u32 ref, u32 freq)
767 struct pll_param pll_param;
769 memset(&pll_param, 0, sizeof(struct pll_param));
771 if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
772 ret = calc_pll_params(ref, freq, &pll_param);
774 printf("Error:Can't find pll parameters: %d\n",
778 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
779 readl(&mxc_ccm->cbcmr))) {
781 return config_pll_clk(PLL1_CLOCK, &pll_param);
784 return config_pll_clk(PLL3_CLOCK, &pll_param);
794 static int config_ddr_clk(u32 emi_clk)
797 s32 shift = 0, clk_sel, div = 1;
798 u32 cbcmr = readl(&mxc_ccm->cbcmr);
800 if (emi_clk > MAX_DDR_CLK) {
801 printf("Warning:DDR clock should not exceed %d MHz\n",
802 MAX_DDR_CLK / SZ_DEC_1M);
803 emi_clk = MAX_DDR_CLK;
806 clk_src = get_periph_clk();
807 /* Find DDR clock input */
808 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
826 if ((clk_src % emi_clk) < 10000000)
827 div = clk_src / emi_clk;
829 div = (clk_src / emi_clk) + 1;
833 clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
834 while (readl(&mxc_ccm->cdhipr) != 0)
836 writel(0x0, &mxc_ccm->ccdr);
842 static int config_ldb_clk(u32 ref, u32 freq)
845 struct pll_param pll_param;
847 memset(&pll_param, 0, sizeof(struct pll_param));
849 ret = calc_pll_params(ref, freq, &pll_param);
851 printf("Error:Can't find pll parameters: %d\n",
856 return config_pll_clk(PLL4_CLOCK, &pll_param);
859 static int config_ldb_clk(u32 ref, u32 freq)
861 /* Platform not supported */
867 * This function assumes the expected core clock has to be changed by
868 * modifying the PLL. This is NOT true always but for most of the times,
869 * it is. So it assumes the PLL output freq is the same as the expected
870 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
871 * In the latter case, it will try to increase the presc value until
872 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
873 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
874 * on the targeted PLL and reference input clock to the PLL. Lastly,
875 * it sets the register based on these values along with the dividers.
876 * Note 1) There is no value checking for the passed-in divider values
877 * so the caller has to make sure those values are sensible.
878 * 2) Also adjust the NFC divider such that the NFC clock doesn't
879 * exceed NFC_CLK_MAX.
880 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
881 * 177MHz for higher voltage, this function fixes the max to 133MHz.
882 * 4) This function should not have allowed diag_printf() calls since
883 * the serial driver has been stoped. But leave then here to allow
884 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
886 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
892 if (config_core_clk(ref, freq))
896 if (config_periph_clk(ref, freq))
900 if (config_ddr_clk(freq))
904 if (config_nfc_clk(freq))
908 if (config_ldb_clk(ref, freq))
912 printf("Warning:Unsupported or invalid clock type\n");
920 * The clock for the external interface can be set to use internal clock
921 * if fuse bank 4, row 3, bit 2 is set.
922 * This is an undocumented feature and it was confirmed by Freescale's support:
923 * Fuses (but not pins) may be used to configure SATA clocks.
924 * Particularly the i.MX53 Fuse_Map contains the next information
925 * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
926 * '00' - 100MHz (External)
927 * '01' - 50MHz (External)
928 * '10' - 120MHz, internal (USB PHY)
931 void mxc_set_sata_internal_clock(void)
934 (u32 *)(IIM_BASE_ADDR + 0x180c);
938 clrsetbits_le32(tmp_base, 0x6, 0x4);
942 #ifndef CONFIG_SPL_BUILD
944 * Dump some core clockes.
946 static int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
950 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
951 printf("PLL1 %8d MHz\n", freq / 1000000);
952 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
953 printf("PLL2 %8d MHz\n", freq / 1000000);
954 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
955 printf("PLL3 %8d MHz\n", freq / 1000000);
957 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
958 printf("PLL4 %8d MHz\n", freq / 1000000);
962 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
963 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
964 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
965 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
966 #ifdef CONFIG_MXC_SPI
967 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
972 /***************************************************/
975 clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,