1 // SPDX-License-Identifier: GPL-2.0+
6 #if defined(CONFIG_MX53)
7 #define MEMCTL_BASE ESDCTL_BASE_ADDR
9 #define MEMCTL_BASE MMDC_P0_BASE_ADDR
11 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
12 static const unsigned char bank_lookup[] = {3, 2};
14 /* these MMDC registers are common to the IMX53 and IMX6 */
15 struct esd_mmdc_regs {
25 #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
26 #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
27 #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
28 #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
29 #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
32 * imx_ddr_size - return size in bytes of DRAM according MMDC config
33 * The MMDC MDCTL register holds the number of bits for row, col, and data
34 * width and the MMDC MDMISC register holds the number of banks. Combine
35 * all these bits to determine the meme size the MMDC has been configured for
37 unsigned imx_ddr_size(void)
39 struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
40 unsigned ctl = readl(&mem->ctl);
41 unsigned misc = readl(&mem->misc);
42 int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
44 bits += ESD_MMDC_CTL_GET_ROW(ctl);
45 bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
46 bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
47 bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
48 bits += ESD_MMDC_CTL_GET_CS1(ctl);
50 /* The MX6 can do only 3840 MiB of DRAM */