arch/arm/mach-imx/imx8m/soc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/mach-imx/hab.h>
  14 #include <asm/mach-imx/boot_mode.h>
  15 #include <asm/mach-imx/syscounter.h>
  16 #include <asm/armv8/mmu.h>
  17 #include <errno.h>
  18 #include <fdt_support.h>
  19 #include <fsl_wdog.h>
  20 #include <imx_sip.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #if defined(CONFIG_SECURE_BOOT)
  25 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  26         .bank = 1,
  27         .word = 3,
  28 };
  29 #endif
  30
  31 int timer_init(void)
  32 {
  33 #ifdef CONFIG_SPL_BUILD
  34         struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  35         unsigned long freq = readl(&sctr->cntfid0);
  36
  37         /* Update with accurate clock frequency */
  38         asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  39
  40         clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  41                         SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  42 #endif
  43
  44         gd->arch.tbl = 0;
  45         gd->arch.tbu = 0;
  46
  47         return 0;
  48 }
  49
  50 void enable_tzc380(void)
  51 {
  52         struct iomuxc_gpr_base_regs *gpr =
  53                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  54
  55         /* Enable TZASC and lock setting */
  56         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  57         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  58         if (IS_ENABLED(CONFIG_IMX8MM))
  59                 setbits_le32(&gpr->gpr[10], BIT(1));
  60         /*
  61          * set Region 0 attribute to allow secure and non-secure
  62          * read/write permission. Found some masters like usb dwc3
  63          * controllers can't work with secure memory.
  64          */
  65         writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
  66 }
  67
  68 void set_wdog_reset(struct wdog_regs *wdog)
  69 {
  70         /*
  71          * Output WDOG_B signal to reset external pmic or POR_B decided by
  72          * the board design. Without external reset, the peripherals/DDR/
  73          * PMIC are not reset, that may cause system working abnormal.
  74          * WDZST bit is write-once only bit. Align this bit in kernel,
  75          * otherwise kernel code will have no chance to set this bit.
  76          */
  77         setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
  78 }
  79
  80 static struct mm_region imx8m_mem_map[] = {
  81         {
  82                 /* ROM */
  83                 .virt = 0x0UL,
  84                 .phys = 0x0UL,
  85                 .size = 0x100000UL,
  86                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  87                          PTE_BLOCK_OUTER_SHARE
  88         }, {
  89                 /* CAAM */
  90                 .virt = 0x100000UL,
  91                 .phys = 0x100000UL,
  92                 .size = 0x8000UL,
  93                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  94                          PTE_BLOCK_NON_SHARE |
  95                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  96         }, {
  97                 /* TCM */
  98                 .virt = 0x7C0000UL,
  99                 .phys = 0x7C0000UL,
 100                 .size = 0x80000UL,
 101                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 102                          PTE_BLOCK_NON_SHARE |
 103                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 104         }, {
 105                 /* OCRAM */
 106                 .virt = 0x900000UL,
 107                 .phys = 0x900000UL,
 108                 .size = 0x200000UL,
 109                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 110                          PTE_BLOCK_OUTER_SHARE
 111         }, {
 112                 /* AIPS */
 113                 .virt = 0xB00000UL,
 114                 .phys = 0xB00000UL,
 115                 .size = 0x3f500000UL,
 116                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 117                          PTE_BLOCK_NON_SHARE |
 118                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 119         }, {
 120                 /* DRAM1 */
 121                 .virt = 0x40000000UL,
 122                 .phys = 0x40000000UL,
 123                 .size = PHYS_SDRAM_SIZE,
 124                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 125                          PTE_BLOCK_OUTER_SHARE
 126 #ifdef PHYS_SDRAM_2_SIZE
 127         }, {
 128                 /* DRAM2 */
 129                 .virt = 0x100000000UL,
 130                 .phys = 0x100000000UL,
 131                 .size = PHYS_SDRAM_2_SIZE,
 132                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 133                          PTE_BLOCK_OUTER_SHARE
 134 #endif
 135         }, {
 136                 /* List terminator */
 137                 0,
 138         }
 139 };
 140
 141 struct mm_region *mem_map = imx8m_mem_map;
 142
 143 void enable_caches(void)
 144 {
 145         /*
 146          * If OPTEE runs, remove OPTEE memory from MMU table to
 147          * avoid speculative prefetch. OPTEE runs at the top of
 148          * the first memory bank
 149          */
 150         if (rom_pointer[1])
 151                 imx8m_mem_map[5].size -= rom_pointer[1];
 152
 153         icache_enable();
 154         dcache_enable();
 155 }
 156
 157 static u32 get_cpu_variant_type(u32 type)
 158 {
 159         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 160         struct fuse_bank *bank = &ocotp->bank[1];
 161         struct fuse_bank1_regs *fuse =
 162                 (struct fuse_bank1_regs *)bank->fuse_regs;
 163
 164         u32 value = readl(&fuse->tester4);
 165
 166         if (type == MXC_CPU_IMX8MM) {
 167                 switch (value & 0x3) {
 168                 case 2:
 169                         if (value & 0x1c0000)
 170                                 return MXC_CPU_IMX8MMDL;
 171                         else
 172                                 return MXC_CPU_IMX8MMD;
 173                 case 3:
 174                         if (value & 0x1c0000)
 175                                 return MXC_CPU_IMX8MMSL;
 176                         else
 177                                 return MXC_CPU_IMX8MMS;
 178                 default:
 179                         if (value & 0x1c0000)
 180                                 return MXC_CPU_IMX8MML;
 181                         break;
 182                 }
 183         }
 184
 185         return type;
 186 }
 187
 188 u32 get_cpu_rev(void)
 189 {
 190         struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
 191         u32 reg = readl(&ana_pll->digprog);
 192         u32 type = (reg >> 16) & 0xff;
 193         u32 major_low = (reg >> 8) & 0xff;
 194         u32 rom_version;
 195
 196         reg &= 0xff;
 197
 198         /* i.MX8MM */
 199         if (major_low == 0x41) {
 200                 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
 201         } else {
 202                 if (reg == CHIP_REV_1_0) {
 203                         /*
 204                          * For B0 chip, the DIGPROG is not updated, still TO1.0.
 205                          * we have to check ROM version further
 206                          */
 207                         rom_version = readl((void __iomem *)ROM_VERSION_A0);
 208                         if (rom_version != CHIP_REV_1_0) {
 209                                 rom_version = readl((void __iomem *)ROM_VERSION_B0);
 210                                 if (rom_version >= CHIP_REV_2_0)
 211                                         reg = CHIP_REV_2_0;
 212                         }
 213                 }
 214         }
 215
 216         return (type << 12) | reg;
 217 }
 218
 219 static void imx_set_wdog_powerdown(bool enable)
 220 {
 221         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 222         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 223         struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
 224
 225         /* Write to the PDE (Power Down Enable) bit */
 226         writew(enable, &wdog1->wmcr);
 227         writew(enable, &wdog2->wmcr);
 228         writew(enable, &wdog3->wmcr);
 229 }
 230
 231 int arch_cpu_init(void)
 232 {
 233         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 234         /*
 235          * Init timer at very early state, because sscg pll setting
 236          * will use it
 237          */
 238         timer_init();
 239
 240         if (IS_ENABLED(CONFIG_SPL_BUILD)) {
 241                 clock_init();
 242                 imx_set_wdog_powerdown(false);
 243         }
 244
 245         if (is_imx8mq()) {
 246                 clock_enable(CCGR_OCOTP, 1);
 247                 if (readl(&ocotp->ctrl) & 0x200)
 248                         writel(0x200, &ocotp->ctrl_clr);
 249         }
 250
 251         return 0;
 252 }
 253
 254 bool is_usb_boot(void)
 255 {
 256         return get_boot_device() == USB_BOOT;
 257 }
 258
 259 #ifdef CONFIG_OF_SYSTEM_SETUP
 260 int ft_system_setup(void *blob, bd_t *bd)
 261 {
 262         int i = 0;
 263         int rc;
 264         int nodeoff;
 265
 266         /* Disable the CPU idle for A0 chip since the HW does not support it */
 267         if (is_soc_rev(CHIP_REV_1_0)) {
 268                 static const char * const nodes_path[] = {
 269                         "/cpus/cpu@0",
 270                         "/cpus/cpu@1",
 271                         "/cpus/cpu@2",
 272                         "/cpus/cpu@3",
 273                 };
 274
 275                 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
 276                         nodeoff = fdt_path_offset(blob, nodes_path[i]);
 277                         if (nodeoff < 0)
 278                                 continue; /* Not found, skip it */
 279
 280                         printf("Found %s node\n", nodes_path[i]);
 281
 282                         rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
 283                         if (rc) {
 284                                 printf("Unable to update property %s:%s, err=%s\n",
 285                                        nodes_path[i], "status", fdt_strerror(rc));
 286                                 return rc;
 287                         }
 288
 289                         printf("Remove %s:%s\n", nodes_path[i],
 290                                "cpu-idle-states");
 291                 }
 292         }
 293
 294         return 0;
 295 }
 296 #endif
 297
 298 void reset_cpu(ulong addr)
 299 {
 300         struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 301
 302         /* Clear WDA to trigger WDOG_B immediately */
 303         writew((WCR_WDE | WCR_SRS), &wdog->wcr);
 304
 305         while (1) {
 306                 /*
 307                  * spin for .5 seconds before reset
 308                  */
 309         }
 310 }