arch/arm/mach-imx/imx8m/soc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/mach-imx/hab.h>
  14 #include <asm/mach-imx/boot_mode.h>
  15 #include <asm/mach-imx/syscounter.h>
  16 #include <asm/armv8/mmu.h>
  17 #include <dm/uclass.h>
  18 #include <errno.h>
  19 #include <fdt_support.h>
  20 #include <fsl_wdog.h>
  21 #include <imx_sip.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #if defined(CONFIG_IMX_HAB)
  26 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  27         .bank = 1,
  28         .word = 3,
  29 };
  30 #endif
  31
  32 int timer_init(void)
  33 {
  34 #ifdef CONFIG_SPL_BUILD
  35         struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  36         unsigned long freq = readl(&sctr->cntfid0);
  37
  38         /* Update with accurate clock frequency */
  39         asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  40
  41         clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  42                         SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  43 #endif
  44
  45         gd->arch.tbl = 0;
  46         gd->arch.tbu = 0;
  47
  48         return 0;
  49 }
  50
  51 void enable_tzc380(void)
  52 {
  53         struct iomuxc_gpr_base_regs *gpr =
  54                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  55
  56         /* Enable TZASC and lock setting */
  57         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  58         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  59         if (is_imx8mm() || is_imx8mn())
  60                 setbits_le32(&gpr->gpr[10], BIT(1));
  61         /*
  62          * set Region 0 attribute to allow secure and non-secure
  63          * read/write permission. Found some masters like usb dwc3
  64          * controllers can't work with secure memory.
  65          */
  66         writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
  67 }
  68
  69 void set_wdog_reset(struct wdog_regs *wdog)
  70 {
  71         /*
  72          * Output WDOG_B signal to reset external pmic or POR_B decided by
  73          * the board design. Without external reset, the peripherals/DDR/
  74          * PMIC are not reset, that may cause system working abnormal.
  75          * WDZST bit is write-once only bit. Align this bit in kernel,
  76          * otherwise kernel code will have no chance to set this bit.
  77          */
  78         setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
  79 }
  80
  81 static struct mm_region imx8m_mem_map[] = {
  82         {
  83                 /* ROM */
  84                 .virt = 0x0UL,
  85                 .phys = 0x0UL,
  86                 .size = 0x100000UL,
  87                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  88                          PTE_BLOCK_OUTER_SHARE
  89         }, {
  90                 /* CAAM */
  91                 .virt = 0x100000UL,
  92                 .phys = 0x100000UL,
  93                 .size = 0x8000UL,
  94                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  95                          PTE_BLOCK_NON_SHARE |
  96                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  97         }, {
  98                 /* TCM */
  99                 .virt = 0x7C0000UL,
 100                 .phys = 0x7C0000UL,
 101                 .size = 0x80000UL,
 102                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 103                          PTE_BLOCK_NON_SHARE |
 104                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 105         }, {
 106                 /* OCRAM */
 107                 .virt = 0x900000UL,
 108                 .phys = 0x900000UL,
 109                 .size = 0x200000UL,
 110                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 111                          PTE_BLOCK_OUTER_SHARE
 112         }, {
 113                 /* AIPS */
 114                 .virt = 0xB00000UL,
 115                 .phys = 0xB00000UL,
 116                 .size = 0x3f500000UL,
 117                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 118                          PTE_BLOCK_NON_SHARE |
 119                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 120         }, {
 121                 /* DRAM1 */
 122                 .virt = 0x40000000UL,
 123                 .phys = 0x40000000UL,
 124                 .size = PHYS_SDRAM_SIZE,
 125                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 126                          PTE_BLOCK_OUTER_SHARE
 127 #ifdef PHYS_SDRAM_2_SIZE
 128         }, {
 129                 /* DRAM2 */
 130                 .virt = 0x100000000UL,
 131                 .phys = 0x100000000UL,
 132                 .size = PHYS_SDRAM_2_SIZE,
 133                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 134                          PTE_BLOCK_OUTER_SHARE
 135 #endif
 136         }, {
 137                 /* List terminator */
 138                 0,
 139         }
 140 };
 141
 142 struct mm_region *mem_map = imx8m_mem_map;
 143
 144 void enable_caches(void)
 145 {
 146         /*
 147          * If OPTEE runs, remove OPTEE memory from MMU table to
 148          * avoid speculative prefetch. OPTEE runs at the top of
 149          * the first memory bank
 150          */
 151         if (rom_pointer[1])
 152                 imx8m_mem_map[5].size -= rom_pointer[1];
 153
 154         icache_enable();
 155         dcache_enable();
 156 }
 157
 158 static u32 get_cpu_variant_type(u32 type)
 159 {
 160         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 161         struct fuse_bank *bank = &ocotp->bank[1];
 162         struct fuse_bank1_regs *fuse =
 163                 (struct fuse_bank1_regs *)bank->fuse_regs;
 164
 165         u32 value = readl(&fuse->tester4);
 166
 167         if (type == MXC_CPU_IMX8MM) {
 168                 switch (value & 0x3) {
 169                 case 2:
 170                         if (value & 0x1c0000)
 171                                 return MXC_CPU_IMX8MMDL;
 172                         else
 173                                 return MXC_CPU_IMX8MMD;
 174                 case 3:
 175                         if (value & 0x1c0000)
 176                                 return MXC_CPU_IMX8MMSL;
 177                         else
 178                                 return MXC_CPU_IMX8MMS;
 179                 default:
 180                         if (value & 0x1c0000)
 181                                 return MXC_CPU_IMX8MML;
 182                         break;
 183                 }
 184         }
 185
 186         return type;
 187 }
 188
 189 u32 get_cpu_rev(void)
 190 {
 191         struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
 192         u32 reg = readl(&ana_pll->digprog);
 193         u32 type = (reg >> 16) & 0xff;
 194         u32 major_low = (reg >> 8) & 0xff;
 195         u32 rom_version;
 196
 197         reg &= 0xff;
 198
 199         /* i.MX8MM */
 200         if (major_low == 0x42) {
 201                 return (MXC_CPU_IMX8MN << 12) | reg;
 202         } else if (major_low == 0x41) {
 203                 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
 204         } else {
 205                 if (reg == CHIP_REV_1_0) {
 206                         /*
 207                          * For B0 chip, the DIGPROG is not updated,
 208                          * it is still TO1.0. we have to check ROM
 209                          * version or OCOTP_READ_FUSE_DATA.
 210                          * 0xff0055aa is magic number for B1.
 211                          */
 212                         if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
 213                                 reg = CHIP_REV_2_1;
 214                         } else {
 215                                 rom_version =
 216                                         readl((void __iomem *)ROM_VERSION_A0);
 217                                 if (rom_version != CHIP_REV_1_0) {
 218                                         rom_version = readl((void __iomem *)ROM_VERSION_B0);
 219                                         if (rom_version == CHIP_REV_2_0)
 220                                                 reg = CHIP_REV_2_0;
 221                                 }
 222                         }
 223                 }
 224         }
 225
 226         return (type << 12) | reg;
 227 }
 228
 229 static void imx_set_wdog_powerdown(bool enable)
 230 {
 231         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 232         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 233         struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
 234
 235         /* Write to the PDE (Power Down Enable) bit */
 236         writew(enable, &wdog1->wmcr);
 237         writew(enable, &wdog2->wmcr);
 238         writew(enable, &wdog3->wmcr);
 239 }
 240
 241 int arch_cpu_init_dm(void)
 242 {
 243         struct udevice *dev;
 244         int ret;
 245
 246         if (CONFIG_IS_ENABLED(CLK)) {
 247                 ret = uclass_get_device_by_name(UCLASS_CLK,
 248                                                 "clock-controller@30380000",
 249                                                 &dev);
 250                 if (ret < 0) {
 251                         printf("Failed to find clock node. Check device tree\n");
 252                         return ret;
 253                 }
 254         }
 255
 256         return 0;
 257 }
 258
 259 int arch_cpu_init(void)
 260 {
 261         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 262         /*
 263          * ROM might disable clock for SCTR,
 264          * enable the clock before timer_init.
 265          */
 266         if (IS_ENABLED(CONFIG_SPL_BUILD))
 267                 clock_enable(CCGR_SCTR, 1);
 268         /*
 269          * Init timer at very early state, because sscg pll setting
 270          * will use it
 271          */
 272         timer_init();
 273
 274         if (IS_ENABLED(CONFIG_SPL_BUILD)) {
 275                 clock_init();
 276                 imx_set_wdog_powerdown(false);
 277         }
 278
 279         if (is_imx8mq()) {
 280                 clock_enable(CCGR_OCOTP, 1);
 281                 if (readl(&ocotp->ctrl) & 0x200)
 282                         writel(0x200, &ocotp->ctrl_clr);
 283         }
 284
 285         return 0;
 286 }
 287
 288 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
 289 struct rom_api *g_rom_api = (struct rom_api *)0x980;
 290
 291 enum boot_device get_boot_device(void)
 292 {
 293         volatile gd_t *pgd = gd;
 294         int ret;
 295         u32 boot;
 296         u16 boot_type;
 297         u8 boot_instance;
 298         enum boot_device boot_dev = SD1_BOOT;
 299
 300         ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
 301                                           ((uintptr_t)&boot) ^ QUERY_BT_DEV);
 302         gd = pgd;
 303
 304         if (ret != ROM_API_OKAY) {
 305                 puts("ROMAPI: failure at query_boot_info\n");
 306                 return -1;
 307         }
 308
 309         boot_type = boot >> 16;
 310         boot_instance = (boot >> 8) & 0xff;
 311
 312         switch (boot_type) {
 313         case BT_DEV_TYPE_SD:
 314                 boot_dev = boot_instance + SD1_BOOT;
 315                 break;
 316         case BT_DEV_TYPE_MMC:
 317                 boot_dev = boot_instance + MMC1_BOOT;
 318                 break;
 319         case BT_DEV_TYPE_NAND:
 320                 boot_dev = NAND_BOOT;
 321                 break;
 322         case BT_DEV_TYPE_FLEXSPINOR:
 323                 boot_dev = QSPI_BOOT;
 324                 break;
 325         case BT_DEV_TYPE_USB:
 326                 boot_dev = USB_BOOT;
 327                 break;
 328         default:
 329                 break;
 330         }
 331
 332         return boot_dev;
 333 }
 334 #endif
 335
 336 bool is_usb_boot(void)
 337 {
 338         return get_boot_device() == USB_BOOT;
 339 }
 340
 341 #ifdef CONFIG_OF_SYSTEM_SETUP
 342 int ft_system_setup(void *blob, bd_t *bd)
 343 {
 344         int i = 0;
 345         int rc;
 346         int nodeoff;
 347
 348         /* Disable the CPU idle for A0 chip since the HW does not support it */
 349         if (is_soc_rev(CHIP_REV_1_0)) {
 350                 static const char * const nodes_path[] = {
 351                         "/cpus/cpu@0",
 352                         "/cpus/cpu@1",
 353                         "/cpus/cpu@2",
 354                         "/cpus/cpu@3",
 355                 };
 356
 357                 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
 358                         nodeoff = fdt_path_offset(blob, nodes_path[i]);
 359                         if (nodeoff < 0)
 360                                 continue; /* Not found, skip it */
 361
 362                         printf("Found %s node\n", nodes_path[i]);
 363
 364                         rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
 365                         if (rc) {
 366                                 printf("Unable to update property %s:%s, err=%s\n",
 367                                        nodes_path[i], "status", fdt_strerror(rc));
 368                                 return rc;
 369                         }
 370
 371                         printf("Remove %s:%s\n", nodes_path[i],
 372                                "cpu-idle-states");
 373                 }
 374         }
 375
 376         return 0;
 377 }
 378 #endif
 379
 380 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET)
 381 void reset_cpu(ulong addr)
 382 {
 383        struct watchdog_regs *wdog = (struct watchdog_regs *)addr;
 384
 385        if (!addr)
 386                wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 387
 388        /* Clear WDA to trigger WDOG_B immediately */
 389        writew((WCR_WDE | WCR_SRS), &wdog->wcr);
 390
 391        while (1) {
 392                /*
 393                 * spin for .5 seconds before reset
 394                 */
 395        }
 396 }
 397 #endif