arch/arm/mach-imx/imx8m/soc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/mach-imx/hab.h>
  14 #include <asm/mach-imx/boot_mode.h>
  15 #include <asm/mach-imx/syscounter.h>
  16 #include <asm/armv8/mmu.h>
  17 #include <errno.h>
  18 #include <fdt_support.h>
  19 #include <fsl_wdog.h>
  20 #include <imx_sip.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #if defined(CONFIG_SECURE_BOOT)
  25 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  26         .bank = 1,
  27         .word = 3,
  28 };
  29 #endif
  30
  31 int timer_init(void)
  32 {
  33 #ifdef CONFIG_SPL_BUILD
  34         struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  35         unsigned long freq = readl(&sctr->cntfid0);
  36
  37         /* Update with accurate clock frequency */
  38         asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  39
  40         clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  41                         SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  42 #endif
  43
  44         gd->arch.tbl = 0;
  45         gd->arch.tbu = 0;
  46
  47         return 0;
  48 }
  49
  50 void enable_tzc380(void)
  51 {
  52         struct iomuxc_gpr_base_regs *gpr =
  53                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  54
  55         /* Enable TZASC and lock setting */
  56         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  57         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  58 }
  59
  60 void set_wdog_reset(struct wdog_regs *wdog)
  61 {
  62         /*
  63          * Output WDOG_B signal to reset external pmic or POR_B decided by
  64          * the board design. Without external reset, the peripherals/DDR/
  65          * PMIC are not reset, that may cause system working abnormal.
  66          * WDZST bit is write-once only bit. Align this bit in kernel,
  67          * otherwise kernel code will have no chance to set this bit.
  68          */
  69         setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
  70 }
  71
  72 static struct mm_region imx8m_mem_map[] = {
  73         {
  74                 /* ROM */
  75                 .virt = 0x0UL,
  76                 .phys = 0x0UL,
  77                 .size = 0x100000UL,
  78                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  79                          PTE_BLOCK_OUTER_SHARE
  80         }, {
  81                 /* CAAM */
  82                 .virt = 0x100000UL,
  83                 .phys = 0x100000UL,
  84                 .size = 0x8000UL,
  85                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  86                          PTE_BLOCK_NON_SHARE |
  87                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  88         }, {
  89                 /* TCM */
  90                 .virt = 0x7C0000UL,
  91                 .phys = 0x7C0000UL,
  92                 .size = 0x80000UL,
  93                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  94                          PTE_BLOCK_NON_SHARE |
  95                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  96         }, {
  97                 /* OCRAM */
  98                 .virt = 0x900000UL,
  99                 .phys = 0x900000UL,
 100                 .size = 0x200000UL,
 101                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 102                          PTE_BLOCK_OUTER_SHARE
 103         }, {
 104                 /* AIPS */
 105                 .virt = 0xB00000UL,
 106                 .phys = 0xB00000UL,
 107                 .size = 0x3f500000UL,
 108                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 109                          PTE_BLOCK_NON_SHARE |
 110                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
 111         }, {
 112                 /* DRAM1 */
 113                 .virt = 0x40000000UL,
 114                 .phys = 0x40000000UL,
 115                 .size = 0xC0000000UL,
 116                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 117                          PTE_BLOCK_OUTER_SHARE
 118         }, {
 119                 /* DRAM2 */
 120                 .virt = 0x100000000UL,
 121                 .phys = 0x100000000UL,
 122                 .size = 0x040000000UL,
 123                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 124                          PTE_BLOCK_OUTER_SHARE
 125         }, {
 126                 /* List terminator */
 127                 0,
 128         }
 129 };
 130
 131 struct mm_region *mem_map = imx8m_mem_map;
 132
 133 static u32 get_cpu_variant_type(u32 type)
 134 {
 135         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 136         struct fuse_bank *bank = &ocotp->bank[1];
 137         struct fuse_bank1_regs *fuse =
 138                 (struct fuse_bank1_regs *)bank->fuse_regs;
 139
 140         u32 value = readl(&fuse->tester4);
 141
 142         if (type == MXC_CPU_IMX8MM) {
 143                 switch (value & 0x3) {
 144                 case 2:
 145                         if (value & 0x1c0000)
 146                                 return MXC_CPU_IMX8MMDL;
 147                         else
 148                                 return MXC_CPU_IMX8MMD;
 149                 case 3:
 150                         if (value & 0x1c0000)
 151                                 return MXC_CPU_IMX8MMSL;
 152                         else
 153                                 return MXC_CPU_IMX8MMS;
 154                 default:
 155                         if (value & 0x1c0000)
 156                                 return MXC_CPU_IMX8MML;
 157                         break;
 158                 }
 159         }
 160
 161         return type;
 162 }
 163
 164 u32 get_cpu_rev(void)
 165 {
 166         struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
 167         u32 reg = readl(&ana_pll->digprog);
 168         u32 type = (reg >> 16) & 0xff;
 169         u32 major_low = (reg >> 8) & 0xff;
 170         u32 rom_version;
 171
 172         reg &= 0xff;
 173
 174         /* i.MX8MM */
 175         if (major_low == 0x41) {
 176                 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
 177         } else {
 178                 if (reg == CHIP_REV_1_0) {
 179                         /*
 180                          * For B0 chip, the DIGPROG is not updated, still TO1.0.
 181                          * we have to check ROM version further
 182                          */
 183                         rom_version = readl((void __iomem *)ROM_VERSION_A0);
 184                         if (rom_version != CHIP_REV_1_0) {
 185                                 rom_version = readl((void __iomem *)ROM_VERSION_B0);
 186                                 if (rom_version >= CHIP_REV_2_0)
 187                                         reg = CHIP_REV_2_0;
 188                         }
 189                 }
 190         }
 191
 192         return (type << 12) | reg;
 193 }
 194
 195 static void imx_set_wdog_powerdown(bool enable)
 196 {
 197         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 198         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 199         struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
 200
 201         /* Write to the PDE (Power Down Enable) bit */
 202         writew(enable, &wdog1->wmcr);
 203         writew(enable, &wdog2->wmcr);
 204         writew(enable, &wdog3->wmcr);
 205 }
 206
 207 int arch_cpu_init(void)
 208 {
 209         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 210         /*
 211          * Init timer at very early state, because sscg pll setting
 212          * will use it
 213          */
 214         timer_init();
 215
 216         if (IS_ENABLED(CONFIG_SPL_BUILD)) {
 217                 clock_init();
 218                 imx_set_wdog_powerdown(false);
 219         }
 220
 221         if (is_imx8mq()) {
 222                 clock_enable(CCGR_OCOTP, 1);
 223                 if (readl(&ocotp->ctrl) & 0x200)
 224                         writel(0x200, &ocotp->ctrl_clr);
 225         }
 226
 227         return 0;
 228 }
 229
 230 bool is_usb_boot(void)
 231 {
 232         return get_boot_device() == USB_BOOT;
 233 }
 234
 235 #ifdef CONFIG_OF_SYSTEM_SETUP
 236 int ft_system_setup(void *blob, bd_t *bd)
 237 {
 238         int i = 0;
 239         int rc;
 240         int nodeoff;
 241
 242         /* Disable the CPU idle for A0 chip since the HW does not support it */
 243         if (is_soc_rev(CHIP_REV_1_0)) {
 244                 static const char * const nodes_path[] = {
 245                         "/cpus/cpu@0",
 246                         "/cpus/cpu@1",
 247                         "/cpus/cpu@2",
 248                         "/cpus/cpu@3",
 249                 };
 250
 251                 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
 252                         nodeoff = fdt_path_offset(blob, nodes_path[i]);
 253                         if (nodeoff < 0)
 254                                 continue; /* Not found, skip it */
 255
 256                         printf("Found %s node\n", nodes_path[i]);
 257
 258                         rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
 259                         if (rc) {
 260                                 printf("Unable to update property %s:%s, err=%s\n",
 261                                        nodes_path[i], "status", fdt_strerror(rc));
 262                                 return rc;
 263                         }
 264
 265                         printf("Remove %s:%s\n", nodes_path[i],
 266                                "cpu-idle-states");
 267                 }
 268         }
 269
 270         return 0;
 271 }
 272 #endif
 273
 274 void reset_cpu(ulong addr)
 275 {
 276         struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 277
 278         /* Clear WDA to trigger WDOG_B immediately */
 279         writew((WCR_WDE | WCR_SRS), &wdog->wcr);
 280
 281         while (1) {
 282                 /*
 283                  * spin for .5 seconds before reset
 284                  */
 285         }
 286 }