arch/arm/mach-imx/imx8m/clock_slice.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/io.h>
  12 #include <errno.h>
  13
  14 static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
  15
  16 #ifdef CONFIG_IMX8MQ
  17 static struct clk_root_map root_array[] = {
  18         {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
  19          {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
  20           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
  21           SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
  22         },
  23         {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
  24          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
  25           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  26           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
  27         },
  28         {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
  29          {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
  30           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
  31           SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
  32         },
  33         {GPU_CORE_CLK_ROOT, CORE_CLOCK_SLICE, 3,
  34          {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  35           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  36           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  37         },
  38         {GPU_SHADER_CLK_ROOT, CORE_CLOCK_SLICE, 4,
  39          {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  40           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  41           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  42         },
  43         {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
  44          {OSC_25M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
  45           SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
  46           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
  47         },
  48         {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
  49          {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  50           SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
  51           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
  52         },
  53         {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
  54          {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  55           SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
  56           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
  57         },
  58         {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
  59          {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
  60           AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  61           SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
  62         },
  63         {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
  64          {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
  65           SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
  66           EXT_CLK_1, EXT_CLK_4}
  67         },
  68         {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
  69          {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
  70           SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
  71           EXT_CLK_1, EXT_CLK_3}
  72         },
  73         {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
  74          {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
  75           SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  76           EXT_CLK_2, EXT_CLK_3}
  77         },
  78         {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
  79          {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
  80           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
  81           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  82         },
  83         {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
  84          {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
  85           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  86           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  87         },
  88         {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
  89          {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
  90           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  91           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  92         },
  93         {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
  94          {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
  95           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
  96           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  97         },
  98         {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
  99          {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
 100           SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
 101           SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
 102         },
 103         {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
 104          {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
 105           SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
 106           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
 107         },
 108         {IPG_CLK_ROOT, IPG_CLOCK_SLICE, 0,
 109          {}
 110         },
 111         {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
 112          {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
 113           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
 114           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
 115         },
 116         {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
 117          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_40M_CLK,
 118           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 119           SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL1_CLK },
 120         },
 121         {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
 122          {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
 123           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_250M_CLK,
 124           SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
 125         },
 126         {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
 127          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 128           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 129           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 130         },
 131         {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
 132          {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 133           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
 134           SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
 135         },
 136         {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
 137          {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 138           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
 139           SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
 140         },
 141         {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
 142          {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 143           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
 144           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
 145         },
 146         {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
 147          {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 148           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
 149           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
 150         },
 151         {PCIE1_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
 152          {OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
 153           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
 154           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
 155         },
 156         {PCIE1_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
 157          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
 158           EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
 159           SYSTEM_PLL1_400M_CLK}
 160         },
 161         {PCIE1_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
 162          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
 163           SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
 164           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
 165         },
 166         {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
 167          {OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
 168           AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
 169           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
 170         },
 171         {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
 172          {OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
 173           AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
 174           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
 175         },
 176         {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
 177          {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 178           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 179           OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
 180         },
 181         {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
 182          {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 183           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 184           OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
 185         },
 186         {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
 187          {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 188           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 189           OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
 190         },
 191         {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
 192          {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 193           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 194           OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
 195         },
 196         {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
 197          {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 198           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 199           OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
 200         },
 201         {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
 202          {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 203           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 204           OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
 205         },
 206         {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
 207          {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 208           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 209           OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
 210         },
 211         {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
 212          {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
 213           VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
 214           OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
 215         },
 216         {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
 217          {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
 218           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 219           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
 220         },
 221         {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
 222          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
 223           EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
 224           VIDEO_PLL_CLK}
 225         },
 226         {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
 227          {OSC_25M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
 228           SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
 229           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 230         },
 231         {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
 232          {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
 233           SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
 234           SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
 235         },
 236         {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
 237          {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
 238           SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
 239           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
 240         },
 241         {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
 242          {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
 243           SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
 244           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
 245         },
 246         {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
 247          {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
 248           SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
 249           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
 250         },
 251         {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
 252          {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 253           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
 254           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
 255         },
 256         {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
 257          {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 258           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
 259           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
 260         },
 261         {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
 262          {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 263           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
 264           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
 265         },
 266         {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
 267          {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 268           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
 269           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
 270         },
 271         {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
 272          {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 273           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 274           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 275         },
 276         {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
 277          {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 278           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 279           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 280         },
 281         {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
 282          {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 283           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 284           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 285         },
 286         {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
 287          {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 288           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 289           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 290         },
 291         {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
 292          {OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
 293           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
 294           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 295         },
 296         {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
 297          {OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
 298           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
 299           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 300         },
 301         {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
 302          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 303           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
 304           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 305         },
 306         {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
 307          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 308           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 309           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 310         },
 311         {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
 312          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 313           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 314           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 315         },
 316         {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
 317          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 318           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
 319           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
 320         },
 321         {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
 322          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 323           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
 324           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
 325         },
 326         {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
 327          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 328           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
 329           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
 330         },
 331         {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
 332          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 333           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
 334           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
 335         },
 336         {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
 337          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 338           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 339           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
 340         },
 341         {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
 342          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 343           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 344           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
 345         },
 346         {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
 347          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 348           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 349           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
 350         },
 351         {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
 352          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 353           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 354           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
 355         },
 356         {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
 357          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 358           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 359           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
 360         },
 361         {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
 362          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 363           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 364           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
 365         },
 366         {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
 367          {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
 368           VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
 369           SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
 370         },
 371         {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
 372          {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
 373           VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
 374           SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
 375         },
 376         {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
 377          {OSC_25M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
 378           SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
 379           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
 380         },
 381         {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
 382          {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, OSC_27M_CLK,
 383           SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
 384           SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
 385         },
 386         {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
 387          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
 388           SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
 389           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
 390         },
 391         {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
 392          {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
 393           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 394           SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 395         },
 396         {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
 397          {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
 398           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 399           EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 400         },
 401         {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
 402          {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
 403           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 404           SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 405         },
 406         {OLD_MIPI_DSI_ESC_CLK_ROOT, IP_CLOCK_SLICE, 57,
 407          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
 408           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 409           SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
 410         },
 411         {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
 412          {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
 413           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 414           SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 415         },
 416         {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
 417          {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
 418           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 419           EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 420         },
 421         {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
 422          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
 423           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 424           SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
 425         },
 426         {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
 427          {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
 428           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 429           SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 430         },
 431         {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
 432          {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
 433           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 434           EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
 435         },
 436         {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
 437          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
 438           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 439           SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
 440         },
 441         {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
 442          {OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
 443           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
 444           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
 445         },
 446         {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
 447          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
 448           EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
 449           EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
 450         },
 451         {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
 452          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
 453           SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
 454           SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
 455         },
 456         {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
 457          {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 458           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 459           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 460         },
 461         {OLD_MIPI_DSI_ESC_RX_ROOT, IP_CLOCK_SLICE, 68,
 462          {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
 463           SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
 464           SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
 465         },
 466         {DISPLAY_HDMI_CLK_ROOT, IP_CLOCK_SLICE, 69,
 467          {OSC_25M_CLK, SYSTEM_PLL1_200M_CLK, SYSTEM_PLL2_200M_CLK,
 468           VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 469           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
 470         },
 471         {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
 472          {DRAM_PLL1_CLK}
 473         },
 474         {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
 475          {DRAM_PLL1_CLK}
 476         },
 477 };
 478 #elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
 479 static struct clk_root_map root_array[] = {
 480         {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
 481          {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
 482           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
 483           SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
 484         },
 485         {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
 486          {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
 487           SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
 488           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
 489         },
 490         {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
 491          {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
 492           SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
 493           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
 494         },
 495         {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
 496          {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
 497           SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
 498           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
 499         },
 500         {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
 501          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
 502           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
 503           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 504         },
 505 #ifdef CONFIG_IMX8MM
 506         {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
 507          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
 508           SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
 509           SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
 510         },
 511 #endif
 512         {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
 513          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
 514           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
 515           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
 516         },
 517         {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
 518          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 519           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 520           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 521         },
 522         {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
 523          {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
 524           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 525           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
 526         },
 527         {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
 528          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
 529           EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
 530           VIDEO_PLL_CLK}
 531         },
 532         {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
 533          {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
 534           SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
 535           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 536         },
 537         {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
 538          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 539           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 540           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 541         },
 542         {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
 543          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 544           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 545           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 546         },
 547         {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
 548          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 549           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 550           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 551         },
 552         {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
 553          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 554           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 555           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 556         },
 557         {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
 558          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 559           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
 560           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 561         },
 562         {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
 563          {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
 564           VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
 565           SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
 566         },
 567         {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
 568          {DRAM_PLL1_CLK}
 569         },
 570 };
 571 #elif defined(CONFIG_IMX8MP)
 572 static struct clk_root_map root_array[] = {
 573         {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
 574          {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
 575           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
 576           SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
 577         },
 578         {ARM_M7_CLK_ROOT, CORE_CLOCK_SLICE, 1,
 579          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
 580           VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 581           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
 582         },
 583         {ML_CLK_ROOT, CORE_CLOCK_SLICE, 2,
 584          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
 585           VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
 586           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
 587         },
 588         {HSIO_AXI_CLK_ROOT, CORE_CLOCK_SLICE, 7,
 589          {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
 590           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, EXT_CLK_2,
 591           EXT_CLK_4, AUDIO_PLL2_CLK}
 592         },
 593         {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
 594          {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
 595           SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK,
 596           VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
 597         },
 598         {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
 599          {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
 600           SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK, AUDIO_PLL1_CLK,
 601           VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
 602         },
 603         {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
 604          {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
 605           SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
 606           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
 607         },
 608         {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
 609          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
 610           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
 611           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 612         },
 613         {NOC_IO_CLK_ROOT, BUS_CLOCK_SLICE, 11,
 614          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
 615           SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
 616           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 617         },
 618         {ML_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 12,
 619          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
 620           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
 621           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 622         },
 623         {ML_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 13,
 624          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
 625           SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
 626           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 627         },
 628         {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
 629          {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
 630           SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
 631           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
 632         },
 633         {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
 634          {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
 635           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
 636           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
 637         },
 638         {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
 639          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 640           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 641           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 642         },
 643         {MEMREPAIR_CLK_ROOT, IP_CLOCK_SLICE, 6,
 644          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 645           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
 646           SYSTEM_PLL1_133M_CLK}
 647         },
 648         {I2C5_CLK_ROOT, IP_CLOCK_SLICE, 9,
 649          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 650           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
 651           SYSTEM_PLL1_133M_CLK}
 652         },
 653         {I2C6_CLK_ROOT, IP_CLOCK_SLICE, 10,
 654          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 655           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
 656           SYSTEM_PLL1_133M_CLK}
 657         },
 658         {ENET_QOS_CLK_ROOT, IP_CLOCK_SLICE, 17,
 659          {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
 660           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 661           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
 662         },
 663         {ENET_QOS_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 18,
 664          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1,
 665           EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, VIDEO_PLL_CLK}
 666         },
 667         {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
 668          {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
 669           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 670           AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
 671         },
 672         {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
 673          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1,
 674           EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, VIDEO_PLL_CLK}
 675         },
 676         {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
 677          {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
 678           SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
 679           VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
 680         },
 681         {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
 682          {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
 683           SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
 684           SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
 685         },
 686         {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
 687          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
 688           SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
 689           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
 690         },
 691         {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
 692          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
 693           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
 694           SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
 695         },
 696         {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
 697          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
 698           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
 699           SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
 700         },
 701         {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
 702          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 703           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
 704           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
 705         },
 706         {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
 707          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 708           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
 709           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
 710         },
 711         {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
 712          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 713           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
 714           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
 715         },
 716         {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
 717          {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
 718           SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
 719           AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
 720         },
 721         {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
 722          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 723           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 724           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 725         },
 726         {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
 727          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 728           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 729           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 730         },
 731         {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
 732          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 733           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 734           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 735         },
 736         {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
 737          {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
 738           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
 739           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 740         },
 741         {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
 742          {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
 743           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
 744           EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
 745         },
 746         {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
 747          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 748           SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
 749           EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
 750         },
 751         {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
 752          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 753           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 754           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 755         },
 756         {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
 757          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 758           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 759           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 760         },
 761         {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
 762          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 763           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
 764           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
 765         },
 766         {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
 767          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 768           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
 769           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
 770         },
 771         {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
 772          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 773           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
 774           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
 775         },
 776         {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
 777          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
 778           SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
 779           SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
 780         },
 781         {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
 782          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 783           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 784           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
 785         },
 786         {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
 787          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 788           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 789           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
 790         },
 791         {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
 792          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 793           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 794           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
 795         },
 796         {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
 797          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 798           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 799           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
 800         },
 801         {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
 802          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 803           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 804           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
 805         },
 806         {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
 807          {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
 808           SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
 809           SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
 810         },
 811         {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
 812          {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
 813           VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
 814           SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
 815         },
 816         {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
 817          {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
 818           VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
 819           SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
 820         },
 821         {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
 822          {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
 823           SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
 824           SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
 825         },
 826         {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
 827          {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
 828           SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
 829           SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
 830         },
 831         {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
 832          {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
 833           SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
 834           SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
 835         },
 836         {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
 837          {DRAM_PLL1_CLK}
 838         },
 839         {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
 840          {DRAM_PLL1_CLK}
 841         },
 842 };
 843 #endif
 844
 845 static int select(enum clk_root_index clock_id)
 846 {
 847         int i, size;
 848         struct clk_root_map *p = root_array;
 849
 850         size = ARRAY_SIZE(root_array);
 851
 852         for (i = 0; i < size; i++, p++) {
 853                 if (clock_id == p->entry)
 854                         return i;
 855         }
 856
 857         return -EINVAL;
 858 }
 859
 860 static void __iomem *get_clk_root_target(enum clk_slice_type slice_type,
 861                                          u32 slice_index)
 862 {
 863         void __iomem *clk_root_target;
 864
 865         switch (slice_type) {
 866         case CORE_CLOCK_SLICE:
 867                 clk_root_target =
 868                 (void __iomem *)&ccm_reg->core_root[slice_index];
 869                 break;
 870         case BUS_CLOCK_SLICE:
 871                 clk_root_target =
 872                         (void __iomem *)&ccm_reg->bus_root[slice_index];
 873                 break;
 874         case IP_CLOCK_SLICE:
 875                 clk_root_target =
 876                         (void __iomem *)&ccm_reg->ip_root[slice_index];
 877                 break;
 878         case AHB_CLOCK_SLICE:
 879                 clk_root_target =
 880                         (void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2];
 881                 break;
 882         case IPG_CLOCK_SLICE:
 883                 clk_root_target =
 884                         (void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2 + 1];
 885                 break;
 886         case CORE_SEL_CLOCK_SLICE:
 887                 clk_root_target = (void __iomem *)&ccm_reg->core_sel;
 888                 break;
 889         case DRAM_SEL_CLOCK_SLICE:
 890                 clk_root_target = (void __iomem *)&ccm_reg->dram_sel;
 891                 break;
 892         default:
 893                 return NULL;
 894         }
 895
 896         return clk_root_target;
 897 }
 898
 899 int clock_get_target_val(enum clk_root_index clock_id, u32 *val)
 900 {
 901         int root_entry;
 902         struct clk_root_map *p;
 903         void __iomem *clk_root_target;
 904
 905         if (clock_id >= CLK_ROOT_MAX)
 906                 return -EINVAL;
 907
 908         root_entry = select(clock_id);
 909         if (root_entry < 0)
 910                 return -EINVAL;
 911
 912         p = &root_array[root_entry];
 913         clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
 914         if (!clk_root_target)
 915                 return -EINVAL;
 916
 917         *val = readl(clk_root_target);
 918
 919         return 0;
 920 }
 921
 922 int clock_set_target_val(enum clk_root_index clock_id, u32 val)
 923 {
 924         int root_entry;
 925         struct clk_root_map *p;
 926         void __iomem *clk_root_target;
 927
 928         if (clock_id >= CLK_ROOT_MAX)
 929                 return -EINVAL;
 930
 931         root_entry = select(clock_id);
 932         if (root_entry < 0)
 933                 return -EINVAL;
 934
 935         p = &root_array[root_entry];
 936         clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
 937         if (!clk_root_target)
 938                 return -EINVAL;
 939
 940         writel(val, clk_root_target);
 941
 942         return 0;
 943 }
 944
 945 int clock_root_enabled(enum clk_root_index clock_id)
 946 {
 947         void __iomem *clk_root_target;
 948         u32 slice_index, slice_type;
 949         u32 val;
 950         int root_entry;
 951
 952         if (clock_id >= CLK_ROOT_MAX)
 953                 return -EINVAL;
 954
 955         root_entry = select(clock_id);
 956         if (root_entry < 0)
 957                 return -EINVAL;
 958
 959         slice_type = root_array[root_entry].slice_type;
 960         slice_index = root_array[root_entry].slice_index;
 961
 962         if ((slice_type == IPG_CLOCK_SLICE) ||
 963             (slice_type == DRAM_SEL_CLOCK_SLICE) ||
 964             (slice_type == CORE_SEL_CLOCK_SLICE)) {
 965                 /*
 966                  * Not supported, from CCM doc
 967                  * TODO
 968                  */
 969                 return 0;
 970         }
 971
 972         clk_root_target = get_clk_root_target(slice_type, slice_index);
 973         if (!clk_root_target)
 974                 return -EINVAL;
 975
 976         val = readl(clk_root_target);
 977
 978         return (val & CLK_ROOT_ON) ? 1 : 0;
 979 }
 980
 981 /* CCGR CLK gate operation */
 982 int clock_enable(enum clk_ccgr_index index, bool enable)
 983 {
 984         void __iomem *ccgr;
 985
 986         if (index >= CCGR_MAX)
 987                 return -EINVAL;
 988
 989         if (enable)
 990                 ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_set;
 991         else
 992                 ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_clr;
 993
 994         writel(CCGR_CLK_ON_MASK, ccgr);
 995
 996         return 0;
 997 }
 998
 999 int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div)
1000 {
1001         u32 val;
1002         int root_entry;
1003         struct clk_root_map *p;
1004         void __iomem *clk_root_target;
1005
1006         if (clock_id >= CLK_ROOT_MAX)
1007                 return -EINVAL;
1008
1009         root_entry = select(clock_id);
1010         if (root_entry < 0)
1011                 return -EINVAL;
1012
1013         p = &root_array[root_entry];
1014
1015         if ((p->slice_type == CORE_CLOCK_SLICE) ||
1016             (p->slice_type == IPG_CLOCK_SLICE) ||
1017             (p->slice_type == CORE_SEL_CLOCK_SLICE) ||
1018             (p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
1019                 *pre_div = 0;
1020                 return 0;
1021         }
1022
1023         clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
1024         if (!clk_root_target)
1025                 return -EINVAL;
1026
1027         val = readl(clk_root_target);
1028         val &= CLK_ROOT_PRE_DIV_MASK;
1029         val >>= CLK_ROOT_PRE_DIV_SHIFT;
1030
1031         *pre_div = val;
1032
1033         return 0;
1034 }
1035
1036 int clock_get_postdiv(enum clk_root_index clock_id,
1037                       enum root_post_div *post_div)
1038 {
1039         u32 val, mask;
1040         int root_entry;
1041         struct clk_root_map *p;
1042         void __iomem *clk_root_target;
1043
1044         if (clock_id >= CLK_ROOT_MAX)
1045                 return -EINVAL;
1046
1047         root_entry = select(clock_id);
1048         if (root_entry < 0)
1049                 return -EINVAL;
1050
1051         p = &root_array[root_entry];
1052
1053         if ((p->slice_type == CORE_SEL_CLOCK_SLICE) ||
1054             (p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
1055                 *post_div = 0;
1056                 return 0;
1057         }
1058
1059         clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
1060         if (!clk_root_target)
1061                 return -EINVAL;
1062
1063         if (p->slice_type == IPG_CLOCK_SLICE)
1064                 mask = CLK_ROOT_IPG_POST_DIV_MASK;
1065         else if (p->slice_type == CORE_CLOCK_SLICE)
1066                 mask = CLK_ROOT_CORE_POST_DIV_MASK;
1067         else
1068                 mask = CLK_ROOT_POST_DIV_MASK;
1069
1070         val = readl(clk_root_target);
1071         val &= mask;
1072         val >>= CLK_ROOT_POST_DIV_SHIFT;
1073
1074         *post_div = val;
1075
1076         return 0;
1077 }
1078
1079 int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src)
1080 {
1081         u32 val;
1082         int root_entry;
1083         struct clk_root_map *p;
1084         void __iomem *clk_root_target;
1085
1086         if (clock_id >= CLK_ROOT_MAX)
1087                 return -EINVAL;
1088
1089         root_entry = select(clock_id);
1090         if (root_entry < 0)
1091                 return -EINVAL;
1092
1093         p = &root_array[root_entry];
1094
1095         clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
1096         if (!clk_root_target)
1097                 return -EINVAL;
1098
1099         val = readl(clk_root_target);
1100         val &= CLK_ROOT_SRC_MUX_MASK;
1101         val >>= CLK_ROOT_SRC_MUX_SHIFT;
1102
1103         *p_clock_src = p->src_mux[val];
1104
1105         return 0;
1106 }