1 // SPDX-License-Identifier: GPL-2.0+
5 * Peng Fan <peng.fan@nxp.com>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/sys_proto.h>
14 #include <linux/iopoll.h>
16 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
18 static u32 get_root_clk(enum clk_root_index clock_id);
20 static u32 decode_frac_pll(enum clk_root_src frac_pll)
22 u32 pll_cfg0, pll_cfg1, pllout;
23 u32 pll_refclk_sel, pll_refclk;
24 u32 divr_val, divq_val, divf_val, divff, divfi;
25 u32 pllout_div_shift, pllout_div_mask, pllout_div;
29 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
30 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
31 pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
32 pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
35 printf("Frac PLL %d not supporte\n", frac_pll);
39 pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
40 pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
43 if (pll_cfg0 & FRAC_PLL_PD_MASK)
46 /* output not enabled */
47 if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
50 pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
52 if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
53 pll_refclk = 25000000u;
54 else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
55 pll_refclk = 27000000u;
56 else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
57 pll_refclk = 27000000u;
61 if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
64 divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
65 FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
66 divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
68 divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
69 FRAC_PLL_FRAC_DIV_CTL_SHIFT;
70 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
72 divf_val = 1 + divfi + divff / (1 << 24);
74 pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
77 return pllout / (pllout_div + 1);
80 static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
82 u32 pll_cfg0, pll_cfg1, pll_cfg2;
83 u32 pll_refclk_sel, pll_refclk;
84 u32 divr1, divr2, divf1, divf2, divq, div;
87 u32 pllout_div_shift, pllout_div_mask, pllout_div;
91 case SYSTEM_PLL1_800M_CLK:
92 case SYSTEM_PLL1_400M_CLK:
93 case SYSTEM_PLL1_266M_CLK:
94 case SYSTEM_PLL1_200M_CLK:
95 case SYSTEM_PLL1_160M_CLK:
96 case SYSTEM_PLL1_133M_CLK:
97 case SYSTEM_PLL1_100M_CLK:
98 case SYSTEM_PLL1_80M_CLK:
99 case SYSTEM_PLL1_40M_CLK:
100 pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
101 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
102 pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
103 pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
104 pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
106 case SYSTEM_PLL2_1000M_CLK:
107 case SYSTEM_PLL2_500M_CLK:
108 case SYSTEM_PLL2_333M_CLK:
109 case SYSTEM_PLL2_250M_CLK:
110 case SYSTEM_PLL2_200M_CLK:
111 case SYSTEM_PLL2_166M_CLK:
112 case SYSTEM_PLL2_125M_CLK:
113 case SYSTEM_PLL2_100M_CLK:
114 case SYSTEM_PLL2_50M_CLK:
115 pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
116 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
117 pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
118 pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
119 pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
121 case SYSTEM_PLL3_CLK:
122 pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
123 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
124 pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
125 pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
126 pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
129 pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
130 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
131 pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
132 pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
133 pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
136 printf("sscg pll %d not supporte\n", sscg_pll);
142 pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
145 case SYSTEM_PLL3_CLK:
146 pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
149 case SYSTEM_PLL2_1000M_CLK:
150 case SYSTEM_PLL1_800M_CLK:
151 pll_clke = SSCG_PLL_CLKE_MASK;
154 case SYSTEM_PLL2_500M_CLK:
155 case SYSTEM_PLL1_400M_CLK:
156 pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
159 case SYSTEM_PLL2_333M_CLK:
160 case SYSTEM_PLL1_266M_CLK:
161 pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
164 case SYSTEM_PLL2_250M_CLK:
165 case SYSTEM_PLL1_200M_CLK:
166 pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
169 case SYSTEM_PLL2_200M_CLK:
170 case SYSTEM_PLL1_160M_CLK:
171 pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
174 case SYSTEM_PLL2_166M_CLK:
175 case SYSTEM_PLL1_133M_CLK:
176 pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
179 case SYSTEM_PLL2_125M_CLK:
180 case SYSTEM_PLL1_100M_CLK:
181 pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
184 case SYSTEM_PLL2_100M_CLK:
185 case SYSTEM_PLL1_80M_CLK:
186 pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
189 case SYSTEM_PLL2_50M_CLK:
190 case SYSTEM_PLL1_40M_CLK:
191 pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
195 printf("sscg pll %d not supporte\n", sscg_pll);
200 if (pll_cfg0 & SSCG_PLL_PD_MASK)
203 /* output not enabled */
204 if ((pll_cfg0 & pll_clke) == 0)
207 pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
208 pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
210 pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
212 if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
213 pll_refclk = 25000000u;
214 else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
215 pll_refclk = 27000000u;
216 else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
217 pll_refclk = 27000000u;
221 /* We assume bypass1/2 are the same value */
222 if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
223 (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
226 divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
227 SSCG_PLL_REF_DIVR1_SHIFT;
228 divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
229 SSCG_PLL_REF_DIVR2_SHIFT;
230 divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
231 SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
232 divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
233 SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
234 divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
235 SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
236 sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
243 pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
244 (divr2 + 1) * (divf2 + 1) / (divq + 1);
246 return pllout / (pllout_div + 1) / div;
249 static u32 get_root_src_clk(enum clk_root_src root_src)
259 return decode_frac_pll(root_src);
260 case SYSTEM_PLL1_800M_CLK:
261 case SYSTEM_PLL1_400M_CLK:
262 case SYSTEM_PLL1_266M_CLK:
263 case SYSTEM_PLL1_200M_CLK:
264 case SYSTEM_PLL1_160M_CLK:
265 case SYSTEM_PLL1_133M_CLK:
266 case SYSTEM_PLL1_100M_CLK:
267 case SYSTEM_PLL1_80M_CLK:
268 case SYSTEM_PLL1_40M_CLK:
269 case SYSTEM_PLL2_1000M_CLK:
270 case SYSTEM_PLL2_500M_CLK:
271 case SYSTEM_PLL2_333M_CLK:
272 case SYSTEM_PLL2_250M_CLK:
273 case SYSTEM_PLL2_200M_CLK:
274 case SYSTEM_PLL2_166M_CLK:
275 case SYSTEM_PLL2_125M_CLK:
276 case SYSTEM_PLL2_100M_CLK:
277 case SYSTEM_PLL2_50M_CLK:
278 case SYSTEM_PLL3_CLK:
279 return decode_sscg_pll(root_src);
280 case ARM_A53_ALT_CLK:
281 return get_root_clk(ARM_A53_CLK_ROOT);
289 static u32 get_root_clk(enum clk_root_index clock_id)
291 enum clk_root_src root_src;
292 u32 post_podf, pre_podf, root_src_clk;
294 if (clock_root_enabled(clock_id) <= 0)
297 if (clock_get_prediv(clock_id, &pre_podf) < 0)
300 if (clock_get_postdiv(clock_id, &post_podf) < 0)
303 if (clock_get_src(clock_id, &root_src) < 0)
306 root_src_clk = get_root_src_clk(root_src);
308 return root_src_clk / (post_podf + 1) / (pre_podf + 1);
311 #ifdef CONFIG_MXC_OCOTP
312 void enable_ocotp_clk(unsigned char enable)
314 clock_enable(CCGR_OCOTP, !!enable);
318 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
320 /* 0 - 3 is valid i2c num */
324 clock_enable(CCGR_I2C1 + i2c_num, !!enable);
329 u32 get_arm_core_clk(void)
331 enum clk_root_src root_src;
334 if (clock_get_src(CORE_SEL_CFG, &root_src) < 0)
337 root_src_clk = get_root_src_clk(root_src);
342 unsigned int mxc_get_clock(enum mxc_clock clk)
348 return get_arm_core_clk();
350 clock_get_target_val(IPG_CLK_ROOT, &val);
352 return get_root_clk(AHB_CLK_ROOT) / (val + 1);
354 return get_root_clk(USDHC1_CLK_ROOT);
356 return get_root_clk(USDHC2_CLK_ROOT);
358 return get_root_clk(clk);
362 u32 imx_get_uartclk(void)
364 return mxc_get_clock(UART1_CLK_ROOT);
367 void mxs_set_lcdclk(u32 base_addr, u32 freq)
370 * LCDIF_PIXEL_CLK: select 800MHz root clock,
371 * select pre divider 8, output is 100 MHz
373 clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
374 CLK_ROOT_SOURCE_SEL(4) |
375 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
378 void init_wdog_clk(void)
380 clock_enable(CCGR_WDOG1, 0);
381 clock_enable(CCGR_WDOG2, 0);
382 clock_enable(CCGR_WDOG3, 0);
383 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
384 CLK_ROOT_SOURCE_SEL(0));
385 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
386 CLK_ROOT_SOURCE_SEL(0));
387 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
388 CLK_ROOT_SOURCE_SEL(0));
389 clock_enable(CCGR_WDOG1, 1);
390 clock_enable(CCGR_WDOG2, 1);
391 clock_enable(CCGR_WDOG3, 1);
395 void init_nand_clk(void)
397 clock_enable(CCGR_RAWNAND, 0);
398 clock_set_target_val(NAND_CLK_ROOT,
399 CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3) |
400 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4));
401 clock_enable(CCGR_RAWNAND, 1);
404 void init_uart_clk(u32 index)
406 /* Set uart clock root 25M OSC */
409 clock_enable(CCGR_UART1, 0);
410 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
411 CLK_ROOT_SOURCE_SEL(0));
412 clock_enable(CCGR_UART1, 1);
415 clock_enable(CCGR_UART2, 0);
416 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
417 CLK_ROOT_SOURCE_SEL(0));
418 clock_enable(CCGR_UART2, 1);
421 clock_enable(CCGR_UART3, 0);
422 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
423 CLK_ROOT_SOURCE_SEL(0));
424 clock_enable(CCGR_UART3, 1);
427 clock_enable(CCGR_UART4, 0);
428 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
429 CLK_ROOT_SOURCE_SEL(0));
430 clock_enable(CCGR_UART4, 1);
433 printf("Invalid uart index\n");
438 void init_clk_usdhc(u32 index)
441 * set usdhc clock root
446 clock_enable(CCGR_USDHC1, 0);
447 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
448 CLK_ROOT_SOURCE_SEL(1));
449 clock_enable(CCGR_USDHC1, 1);
452 clock_enable(CCGR_USDHC2, 0);
453 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
454 CLK_ROOT_SOURCE_SEL(1));
455 clock_enable(CCGR_USDHC2, 1);
458 printf("Invalid usdhc index\n");
463 int set_clk_qspi(void)
469 clock_enable(CCGR_QSPI, 0);
470 clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
471 CLK_ROOT_SOURCE_SEL(7));
472 clock_enable(CCGR_QSPI, 1);
477 #ifdef CONFIG_FEC_MXC
478 int set_clk_enet(enum enet_freq type)
485 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
488 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
491 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
497 /* disable the clock first */
498 clock_enable(CCGR_ENET1, 0);
499 clock_enable(CCGR_SIM_ENET, 0);
501 /* set enet axi clock 266Mhz */
502 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
503 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
504 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
505 clock_set_target_val(ENET_AXI_CLK_ROOT, target);
507 target = CLK_ROOT_ON | enet1_ref |
508 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
509 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
510 clock_set_target_val(ENET_REF_CLK_ROOT, target);
512 target = CLK_ROOT_ON |
513 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
514 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
515 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
516 clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
519 clock_enable(CCGR_SIM_ENET, 1);
520 clock_enable(CCGR_ENET1, 1);
526 u32 imx_get_fecclk(void)
528 return get_root_clk(ENET_AXI_CLK_ROOT);
531 static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
532 DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
534 DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
536 DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
540 void dram_enable_bypass(ulong clk_val)
543 struct dram_bypass_clk_setting *config;
545 for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
546 if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
550 if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
551 printf("No matched freq table %lu\n", clk_val);
555 config = &imx8mq_dram_bypass_tbl[i];
557 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
558 CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
559 CLK_ROOT_PRE_DIV(config->alt_pre_div));
560 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
561 CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
562 CLK_ROOT_PRE_DIV(config->apb_pre_div));
563 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
564 CLK_ROOT_SOURCE_SEL(1));
567 void dram_disable_bypass(void)
569 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
570 CLK_ROOT_SOURCE_SEL(0));
571 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
572 CLK_ROOT_SOURCE_SEL(4) |
573 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
576 #ifdef CONFIG_SPL_BUILD
577 void dram_pll_init(ulong pll_val)
580 void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
581 void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
584 setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
585 setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
589 val = readl(pll_cfg_reg2);
590 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
591 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
592 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
593 SSCG_PLL_REF_DIVR2_MASK);
594 val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
595 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
596 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
597 val |= SSCG_PLL_REF_DIVR2_VAL(29);
598 writel(val, pll_cfg_reg2);
601 val = readl(pll_cfg_reg2);
602 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
603 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
604 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
605 SSCG_PLL_REF_DIVR2_MASK);
606 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
607 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
608 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
609 val |= SSCG_PLL_REF_DIVR2_VAL(29);
610 writel(val, pll_cfg_reg2);
613 val = readl(pll_cfg_reg2);
614 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
615 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
616 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
617 SSCG_PLL_REF_DIVR2_MASK);
618 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
619 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
620 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
621 val |= SSCG_PLL_REF_DIVR2_VAL(29);
622 writel(val, pll_cfg_reg2);
625 val = readl(pll_cfg_reg2);
626 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
627 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
628 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
629 SSCG_PLL_REF_DIVR2_MASK);
630 val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
631 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
632 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
633 val |= SSCG_PLL_REF_DIVR2_VAL(30);
634 writel(val, pll_cfg_reg2);
640 /* Clear power down bit */
641 clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
642 /* Eanble ARM_PLL/SYS_PLL */
643 setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
646 clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
648 clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
650 while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
654 static int frac_pll_init(u32 pll, enum frac_pll_out_val val)
656 void __iomem *pll_cfg0, __iomem *pll_cfg1;
657 u32 val_cfg0, val_cfg1, divq;
662 pll_cfg0 = &ana_pll->arm_pll_cfg0;
663 pll_cfg1 = &ana_pll->arm_pll_cfg1;
665 if (val == FRAC_PLL_OUT_1000M) {
666 val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
669 val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
672 val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
673 FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
674 FRAC_PLL_REFCLK_DIV_VAL(4) |
675 FRAC_PLL_OUTPUT_DIV_VAL(divq);
681 /* bypass the clock */
682 setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
684 writel(val_cfg1, pll_cfg1);
685 writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
686 val_cfg0 = readl(pll_cfg0);
687 /* unbypass the clock */
688 clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
689 ret = readl_poll_timeout(pll_cfg0, val_cfg0,
690 val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
692 printf("%s timeout\n", __func__);
693 clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
703 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
704 CLK_ROOT_SOURCE_SEL(0));
707 * 8MQ only supports two grades: consumer and industrial.
708 * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
710 grade = get_cpu_temp_grade(NULL, NULL);
712 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
714 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_800M);
716 /* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */
717 clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1));
720 * According to ANAMIX SPEC
721 * sys pll1 fixed at 800MHz
722 * sys pll2 fixed at 1GHz
723 * Here we only enable the outputs.
725 setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
726 SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
727 SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
728 SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
729 SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
731 setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
732 SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
733 SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
734 SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
735 SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
737 clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
738 CLK_ROOT_SOURCE_SEL(1));
741 clock_enable(CCGR_TSENSOR, 1);
742 clock_enable(CCGR_OCOTP, 1);
744 /* config GIC ROOT to sys_pll2_200m */
745 clock_enable(CCGR_GIC, 0);
746 clock_set_target_val(GIC_CLK_ROOT,
747 CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
748 clock_enable(CCGR_GIC, 1);
757 #ifndef CONFIG_SPL_BUILD
758 static int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
763 freq = decode_frac_pll(ARM_PLL_CLK);
764 printf("ARM_PLL %8d MHz\n", freq / 1000000);
765 freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
766 printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
767 freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
768 printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
769 freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
770 printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
771 freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
772 printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
773 freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
774 printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
775 freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
776 printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
777 freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
778 printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
779 freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
780 printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
781 freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
782 printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
783 freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
784 printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
785 freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
786 printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
787 freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
788 printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
789 freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
790 printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
791 freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
792 printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
793 freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
794 printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
795 freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
796 printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
797 freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
798 printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
799 freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
800 printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
801 freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
802 printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
803 freq = mxc_get_clock(UART1_CLK_ROOT);
804 printf("UART1 %8d MHz\n", freq / 1000000);
805 freq = mxc_get_clock(USDHC1_CLK_ROOT);
806 printf("USDHC1 %8d MHz\n", freq / 1000000);
807 freq = mxc_get_clock(QSPI_CLK_ROOT);
808 printf("QSPI %8d MHz\n", freq / 1000000);
813 clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,