arch/arm/mach-imx/imx8m/clock_imx8mq.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <errno.h>
  14 #include <linux/iopoll.h>
  15
  16 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  17
  18 static u32 decode_frac_pll(enum clk_root_src frac_pll)
  19 {
  20         u32 pll_cfg0, pll_cfg1, pllout;
  21         u32 pll_refclk_sel, pll_refclk;
  22         u32 divr_val, divq_val, divf_val, divff, divfi;
  23         u32 pllout_div_shift, pllout_div_mask, pllout_div;
  24
  25         switch (frac_pll) {
  26         case ARM_PLL_CLK:
  27                 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
  28                 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
  29                 pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
  30                 pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
  31                 break;
  32         default:
  33                 printf("Frac PLL %d not supporte\n", frac_pll);
  34                 return 0;
  35         }
  36
  37         pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
  38         pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
  39
  40         /* Power down */
  41         if (pll_cfg0 & FRAC_PLL_PD_MASK)
  42                 return 0;
  43
  44         /* output not enabled */
  45         if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
  46                 return 0;
  47
  48         pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
  49
  50         if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
  51                 pll_refclk = 25000000u;
  52         else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
  53                 pll_refclk = 27000000u;
  54         else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
  55                 pll_refclk = 27000000u;
  56         else
  57                 pll_refclk = 0;
  58
  59         if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
  60                 return pll_refclk;
  61
  62         divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
  63                 FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
  64         divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
  65
  66         divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
  67                 FRAC_PLL_FRAC_DIV_CTL_SHIFT;
  68         divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
  69
  70         divf_val = 1 + divfi + divff / (1 << 24);
  71
  72         pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
  73                 ((divq_val + 1) * 2);
  74
  75         return pllout / (pllout_div + 1);
  76 }
  77
  78 static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
  79 {
  80         u32 pll_cfg0, pll_cfg1, pll_cfg2;
  81         u32 pll_refclk_sel, pll_refclk;
  82         u32 divr1, divr2, divf1, divf2, divq, div;
  83         u32 sse;
  84         u32 pll_clke;
  85         u32 pllout_div_shift, pllout_div_mask, pllout_div;
  86         u32 pllout;
  87
  88         switch (sscg_pll) {
  89         case SYSTEM_PLL1_800M_CLK:
  90         case SYSTEM_PLL1_400M_CLK:
  91         case SYSTEM_PLL1_266M_CLK:
  92         case SYSTEM_PLL1_200M_CLK:
  93         case SYSTEM_PLL1_160M_CLK:
  94         case SYSTEM_PLL1_133M_CLK:
  95         case SYSTEM_PLL1_100M_CLK:
  96         case SYSTEM_PLL1_80M_CLK:
  97         case SYSTEM_PLL1_40M_CLK:
  98                 pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
  99                 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
 100                 pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
 101                 pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
 102                 pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
 103                 break;
 104         case SYSTEM_PLL2_1000M_CLK:
 105         case SYSTEM_PLL2_500M_CLK:
 106         case SYSTEM_PLL2_333M_CLK:
 107         case SYSTEM_PLL2_250M_CLK:
 108         case SYSTEM_PLL2_200M_CLK:
 109         case SYSTEM_PLL2_166M_CLK:
 110         case SYSTEM_PLL2_125M_CLK:
 111         case SYSTEM_PLL2_100M_CLK:
 112         case SYSTEM_PLL2_50M_CLK:
 113                 pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
 114                 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
 115                 pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
 116                 pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
 117                 pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
 118                 break;
 119         case SYSTEM_PLL3_CLK:
 120                 pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
 121                 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
 122                 pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
 123                 pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
 124                 pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
 125                 break;
 126         case DRAM_PLL1_CLK:
 127                 pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
 128                 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
 129                 pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
 130                 pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
 131                 pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
 132                 break;
 133         default:
 134                 printf("sscg pll %d not supporte\n", sscg_pll);
 135                 return 0;
 136         }
 137
 138         switch (sscg_pll) {
 139         case DRAM_PLL1_CLK:
 140                 pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
 141                 div = 1;
 142                 break;
 143         case SYSTEM_PLL3_CLK:
 144                 pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
 145                 div = 1;
 146                 break;
 147         case SYSTEM_PLL2_1000M_CLK:
 148         case SYSTEM_PLL1_800M_CLK:
 149                 pll_clke = SSCG_PLL_CLKE_MASK;
 150                 div = 1;
 151                 break;
 152         case SYSTEM_PLL2_500M_CLK:
 153         case SYSTEM_PLL1_400M_CLK:
 154                 pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
 155                 div = 2;
 156                 break;
 157         case SYSTEM_PLL2_333M_CLK:
 158         case SYSTEM_PLL1_266M_CLK:
 159                 pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
 160                 div = 3;
 161                 break;
 162         case SYSTEM_PLL2_250M_CLK:
 163         case SYSTEM_PLL1_200M_CLK:
 164                 pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
 165                 div = 4;
 166                 break;
 167         case SYSTEM_PLL2_200M_CLK:
 168         case SYSTEM_PLL1_160M_CLK:
 169                 pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
 170                 div = 5;
 171                 break;
 172         case SYSTEM_PLL2_166M_CLK:
 173         case SYSTEM_PLL1_133M_CLK:
 174                 pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
 175                 div = 6;
 176                 break;
 177         case SYSTEM_PLL2_125M_CLK:
 178         case SYSTEM_PLL1_100M_CLK:
 179                 pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
 180                 div = 8;
 181                 break;
 182         case SYSTEM_PLL2_100M_CLK:
 183         case SYSTEM_PLL1_80M_CLK:
 184                 pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
 185                 div = 10;
 186                 break;
 187         case SYSTEM_PLL2_50M_CLK:
 188         case SYSTEM_PLL1_40M_CLK:
 189                 pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
 190                 div = 20;
 191                 break;
 192         default:
 193                 printf("sscg pll %d not supporte\n", sscg_pll);
 194                 return 0;
 195         }
 196
 197         /* Power down */
 198         if (pll_cfg0 & SSCG_PLL_PD_MASK)
 199                 return 0;
 200
 201         /* output not enabled */
 202         if ((pll_cfg0 & pll_clke) == 0)
 203                 return 0;
 204
 205         pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
 206         pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
 207
 208         pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
 209
 210         if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
 211                 pll_refclk = 25000000u;
 212         else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
 213                 pll_refclk = 27000000u;
 214         else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
 215                 pll_refclk = 27000000u;
 216         else
 217                 pll_refclk = 0;
 218
 219         /* We assume bypass1/2 are the same value */
 220         if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
 221             (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
 222                 return pll_refclk;
 223
 224         divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
 225                 SSCG_PLL_REF_DIVR1_SHIFT;
 226         divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
 227                 SSCG_PLL_REF_DIVR2_SHIFT;
 228         divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
 229                 SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
 230         divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
 231                 SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
 232         divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
 233                 SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
 234         sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
 235
 236         if (sse)
 237                 sse = 8;
 238         else
 239                 sse = 2;
 240
 241         pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
 242                 (divr2 + 1) * (divf2 + 1) / (divq + 1);
 243
 244         return pllout / (pllout_div + 1) / div;
 245 }
 246
 247 static u32 get_root_src_clk(enum clk_root_src root_src)
 248 {
 249         switch (root_src) {
 250         case OSC_25M_CLK:
 251                 return 25000000;
 252         case OSC_27M_CLK:
 253                 return 27000000;
 254         case OSC_32K_CLK:
 255                 return 32768;
 256         case ARM_PLL_CLK:
 257                 return decode_frac_pll(root_src);
 258         case SYSTEM_PLL1_800M_CLK:
 259         case SYSTEM_PLL1_400M_CLK:
 260         case SYSTEM_PLL1_266M_CLK:
 261         case SYSTEM_PLL1_200M_CLK:
 262         case SYSTEM_PLL1_160M_CLK:
 263         case SYSTEM_PLL1_133M_CLK:
 264         case SYSTEM_PLL1_100M_CLK:
 265         case SYSTEM_PLL1_80M_CLK:
 266         case SYSTEM_PLL1_40M_CLK:
 267         case SYSTEM_PLL2_1000M_CLK:
 268         case SYSTEM_PLL2_500M_CLK:
 269         case SYSTEM_PLL2_333M_CLK:
 270         case SYSTEM_PLL2_250M_CLK:
 271         case SYSTEM_PLL2_200M_CLK:
 272         case SYSTEM_PLL2_166M_CLK:
 273         case SYSTEM_PLL2_125M_CLK:
 274         case SYSTEM_PLL2_100M_CLK:
 275         case SYSTEM_PLL2_50M_CLK:
 276         case SYSTEM_PLL3_CLK:
 277                 return decode_sscg_pll(root_src);
 278         default:
 279                 return 0;
 280         }
 281
 282         return 0;
 283 }
 284
 285 static u32 get_root_clk(enum clk_root_index clock_id)
 286 {
 287         enum clk_root_src root_src;
 288         u32 post_podf, pre_podf, root_src_clk;
 289
 290         if (clock_root_enabled(clock_id) <= 0)
 291                 return 0;
 292
 293         if (clock_get_prediv(clock_id, &pre_podf) < 0)
 294                 return 0;
 295
 296         if (clock_get_postdiv(clock_id, &post_podf) < 0)
 297                 return 0;
 298
 299         if (clock_get_src(clock_id, &root_src) < 0)
 300                 return 0;
 301
 302         root_src_clk = get_root_src_clk(root_src);
 303
 304         return root_src_clk / (post_podf + 1) / (pre_podf + 1);
 305 }
 306
 307 #ifdef CONFIG_MXC_OCOTP
 308 void enable_ocotp_clk(unsigned char enable)
 309 {
 310         clock_enable(CCGR_OCOTP, !!enable);
 311 }
 312 #endif
 313
 314 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
 315 {
 316         /* 0 - 3 is valid i2c num */
 317         if (i2c_num > 3)
 318                 return -EINVAL;
 319
 320         clock_enable(CCGR_I2C1 + i2c_num, !!enable);
 321
 322         return 0;
 323 }
 324
 325 unsigned int mxc_get_clock(enum mxc_clock clk)
 326 {
 327         u32 val;
 328
 329         switch(clk) {
 330         case MXC_ARM_CLK:
 331                 return get_root_clk(ARM_A53_CLK_ROOT);
 332         case MXC_IPG_CLK:
 333                 clock_get_target_val(IPG_CLK_ROOT, &val);
 334                 val = val & 0x3;
 335                 return get_root_clk(AHB_CLK_ROOT) / (val + 1);
 336         case MXC_ESDHC_CLK:
 337                 return get_root_clk(USDHC1_CLK_ROOT);
 338         case MXC_ESDHC2_CLK:
 339                 return get_root_clk(USDHC2_CLK_ROOT);
 340         default:
 341                 return get_root_clk(clk);
 342         }
 343 }
 344
 345 u32 imx_get_uartclk(void)
 346 {
 347         return mxc_get_clock(UART1_CLK_ROOT);
 348 }
 349
 350 void mxs_set_lcdclk(u32 base_addr, u32 freq)
 351 {
 352         /*
 353          * LCDIF_PIXEL_CLK: select 800MHz root clock,
 354          * select pre divider 8, output is 100 MHz
 355          */
 356         clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
 357                              CLK_ROOT_SOURCE_SEL(4) |
 358                              CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
 359 }
 360
 361 void init_wdog_clk(void)
 362 {
 363         clock_enable(CCGR_WDOG1, 0);
 364         clock_enable(CCGR_WDOG2, 0);
 365         clock_enable(CCGR_WDOG3, 0);
 366         clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
 367                              CLK_ROOT_SOURCE_SEL(0));
 368         clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
 369                              CLK_ROOT_SOURCE_SEL(0));
 370         clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
 371                              CLK_ROOT_SOURCE_SEL(0));
 372         clock_enable(CCGR_WDOG1, 1);
 373         clock_enable(CCGR_WDOG2, 1);
 374         clock_enable(CCGR_WDOG3, 1);
 375 }
 376
 377
 378 void init_nand_clk(void)
 379 {
 380         clock_enable(CCGR_RAWNAND, 0);
 381         clock_set_target_val(NAND_CLK_ROOT,
 382                              CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3) |
 383                              CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4));
 384         clock_enable(CCGR_RAWNAND, 1);
 385 }
 386
 387 void init_uart_clk(u32 index)
 388 {
 389         /* Set uart clock root 25M OSC */
 390         switch (index) {
 391         case 0:
 392                 clock_enable(CCGR_UART1, 0);
 393                 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
 394                                      CLK_ROOT_SOURCE_SEL(0));
 395                 clock_enable(CCGR_UART1, 1);
 396                 return;
 397         case 1:
 398                 clock_enable(CCGR_UART2, 0);
 399                 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
 400                                      CLK_ROOT_SOURCE_SEL(0));
 401                 clock_enable(CCGR_UART2, 1);
 402                 return;
 403         case 2:
 404                 clock_enable(CCGR_UART3, 0);
 405                 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
 406                                      CLK_ROOT_SOURCE_SEL(0));
 407                 clock_enable(CCGR_UART3, 1);
 408                 return;
 409         case 3:
 410                 clock_enable(CCGR_UART4, 0);
 411                 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
 412                                      CLK_ROOT_SOURCE_SEL(0));
 413                 clock_enable(CCGR_UART4, 1);
 414                 return;
 415         default:
 416                 printf("Invalid uart index\n");
 417                 return;
 418         }
 419 }
 420
 421 void init_clk_usdhc(u32 index)
 422 {
 423         /*
 424          * set usdhc clock root
 425          * sys pll1 400M
 426          */
 427         switch (index) {
 428         case 0:
 429                 clock_enable(CCGR_USDHC1, 0);
 430                 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
 431                                      CLK_ROOT_SOURCE_SEL(1) |
 432                                      CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
 433                 clock_enable(CCGR_USDHC1, 1);
 434                 return;
 435         case 1:
 436                 clock_enable(CCGR_USDHC2, 0);
 437                 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
 438                                      CLK_ROOT_SOURCE_SEL(1) |
 439                                      CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
 440                 clock_enable(CCGR_USDHC2, 1);
 441                 return;
 442         default:
 443                 printf("Invalid usdhc index\n");
 444                 return;
 445         }
 446 }
 447
 448 int set_clk_qspi(void)
 449 {
 450         /*
 451          * set qspi root
 452          * sys pll1 100M
 453          */
 454         clock_enable(CCGR_QSPI, 0);
 455         clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
 456                              CLK_ROOT_SOURCE_SEL(7));
 457         clock_enable(CCGR_QSPI, 1);
 458
 459         return 0;
 460 }
 461
 462 #ifdef CONFIG_FEC_MXC
 463 int set_clk_enet(enum enet_freq type)
 464 {
 465         u32 target;
 466         u32 enet1_ref;
 467
 468         switch (type) {
 469         case ENET_125MHZ:
 470                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
 471                 break;
 472         case ENET_50MHZ:
 473                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
 474                 break;
 475         case ENET_25MHZ:
 476                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
 477                 break;
 478         default:
 479                 return -EINVAL;
 480         }
 481
 482         /* disable the clock first */
 483         clock_enable(CCGR_ENET1, 0);
 484         clock_enable(CCGR_SIM_ENET, 0);
 485
 486         /* set enet axi clock 266Mhz */
 487         target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
 488                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 489                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 490         clock_set_target_val(ENET_AXI_CLK_ROOT, target);
 491
 492         target = CLK_ROOT_ON | enet1_ref |
 493                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 494                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 495         clock_set_target_val(ENET_REF_CLK_ROOT, target);
 496
 497         target = CLK_ROOT_ON |
 498                 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
 499                 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 500                 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
 501         clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
 502
 503         /* enable clock */
 504         clock_enable(CCGR_SIM_ENET, 1);
 505         clock_enable(CCGR_ENET1, 1);
 506
 507         return 0;
 508 }
 509 #endif
 510
 511 u32 imx_get_fecclk(void)
 512 {
 513         return get_root_clk(ENET_AXI_CLK_ROOT);
 514 }
 515
 516 static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
 517         DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
 518                                 CLK_ROOT_PRE_DIV2),
 519         DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
 520                                 CLK_ROOT_PRE_DIV2),
 521         DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
 522                                 CLK_ROOT_PRE_DIV2),
 523 };
 524
 525 void dram_enable_bypass(ulong clk_val)
 526 {
 527         int i;
 528         struct dram_bypass_clk_setting *config;
 529
 530         for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
 531                 if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
 532                         break;
 533         }
 534
 535         if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
 536                 printf("No matched freq table %lu\n", clk_val);
 537                 return;
 538         }
 539
 540         config = &imx8mq_dram_bypass_tbl[i];
 541
 542         clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
 543                              CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
 544                              CLK_ROOT_PRE_DIV(config->alt_pre_div));
 545         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 546                              CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
 547                              CLK_ROOT_PRE_DIV(config->apb_pre_div));
 548         clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
 549                              CLK_ROOT_SOURCE_SEL(1));
 550 }
 551
 552 void dram_disable_bypass(void)
 553 {
 554         clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
 555                              CLK_ROOT_SOURCE_SEL(0));
 556         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 557                              CLK_ROOT_SOURCE_SEL(4) |
 558                              CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
 559 }
 560
 561 #ifdef CONFIG_SPL_BUILD
 562 void dram_pll_init(ulong pll_val)
 563 {
 564         u32 val;
 565         void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
 566         void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
 567
 568         /* Bypass */
 569         setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
 570         setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
 571
 572         switch (pll_val) {
 573         case MHZ(800):
 574                 val = readl(pll_cfg_reg2);
 575                 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
 576                          SSCG_PLL_FEEDBACK_DIV_F2_MASK |
 577                          SSCG_PLL_FEEDBACK_DIV_F1_MASK |
 578                          SSCG_PLL_REF_DIVR2_MASK);
 579                 val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
 580                 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
 581                 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
 582                 val |= SSCG_PLL_REF_DIVR2_VAL(29);
 583                 writel(val, pll_cfg_reg2);
 584                 break;
 585         case MHZ(600):
 586                 val = readl(pll_cfg_reg2);
 587                 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
 588                          SSCG_PLL_FEEDBACK_DIV_F2_MASK |
 589                          SSCG_PLL_FEEDBACK_DIV_F1_MASK |
 590                          SSCG_PLL_REF_DIVR2_MASK);
 591                 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
 592                 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
 593                 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
 594                 val |= SSCG_PLL_REF_DIVR2_VAL(29);
 595                 writel(val, pll_cfg_reg2);
 596                 break;
 597         case MHZ(400):
 598                 val = readl(pll_cfg_reg2);
 599                 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
 600                          SSCG_PLL_FEEDBACK_DIV_F2_MASK |
 601                          SSCG_PLL_FEEDBACK_DIV_F1_MASK |
 602                          SSCG_PLL_REF_DIVR2_MASK);
 603                 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
 604                 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
 605                 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
 606                 val |= SSCG_PLL_REF_DIVR2_VAL(29);
 607                 writel(val, pll_cfg_reg2);
 608                 break;
 609         case MHZ(167):
 610                 val = readl(pll_cfg_reg2);
 611                 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
 612                          SSCG_PLL_FEEDBACK_DIV_F2_MASK |
 613                          SSCG_PLL_FEEDBACK_DIV_F1_MASK |
 614                          SSCG_PLL_REF_DIVR2_MASK);
 615                 val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
 616                 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
 617                 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
 618                 val |= SSCG_PLL_REF_DIVR2_VAL(30);
 619                 writel(val, pll_cfg_reg2);
 620                 break;
 621         default:
 622                 break;
 623         }
 624
 625         /* Clear power down bit */
 626         clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
 627         /* Eanble ARM_PLL/SYS_PLL  */
 628         setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
 629
 630         /* Clear bypass */
 631         clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
 632         __udelay(100);
 633         clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
 634         /* Wait lock */
 635         while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
 636                 ;
 637 }
 638
 639 static int frac_pll_init(u32 pll, enum frac_pll_out_val val)
 640 {
 641         void __iomem *pll_cfg0, __iomem *pll_cfg1;
 642         u32 val_cfg0, val_cfg1;
 643         int ret;
 644
 645         switch (pll) {
 646         case ANATOP_ARM_PLL:
 647                 pll_cfg0 = &ana_pll->arm_pll_cfg0;
 648                 pll_cfg1 = &ana_pll->arm_pll_cfg1;
 649
 650                 if (val == FRAC_PLL_OUT_1000M)
 651                         val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
 652                 else
 653                         val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
 654                 val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
 655                         FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
 656                         FRAC_PLL_REFCLK_DIV_VAL(4) |
 657                         FRAC_PLL_OUTPUT_DIV_VAL(0);
 658                 break;
 659         default:
 660                 return -EINVAL;
 661         }
 662
 663         /* bypass the clock */
 664         setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
 665         /* Set the value */
 666         writel(val_cfg1, pll_cfg1);
 667         writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
 668         val_cfg0 = readl(pll_cfg0);
 669         /* unbypass the clock */
 670         clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
 671         ret = readl_poll_timeout(pll_cfg0, val_cfg0,
 672                                  val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
 673         if (ret)
 674                 printf("%s timeout\n", __func__);
 675         clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
 676
 677         return 0;
 678 }
 679
 680
 681 int clock_init(void)
 682 {
 683         u32 grade;
 684
 685         clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
 686                              CLK_ROOT_SOURCE_SEL(0));
 687
 688         /*
 689          * 8MQ only supports two grades: consumer and industrial.
 690          * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
 691          */
 692         grade = get_cpu_temp_grade(NULL, NULL);
 693         if (!grade) {
 694                 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
 695                 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
 696                              CLK_ROOT_SOURCE_SEL(1) |
 697                              CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
 698         } else {
 699                 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M);
 700                 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
 701                              CLK_ROOT_SOURCE_SEL(1) |
 702                              CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
 703         }
 704         /*
 705          * According to ANAMIX SPEC
 706          * sys pll1 fixed at 800MHz
 707          * sys pll2 fixed at 1GHz
 708          * Here we only enable the outputs.
 709          */
 710         setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
 711                      SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
 712                      SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
 713                      SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
 714                      SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
 715
 716         setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
 717                      SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
 718                      SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
 719                      SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
 720                      SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
 721
 722         clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
 723                              CLK_ROOT_SOURCE_SEL(1));
 724
 725         init_wdog_clk();
 726         clock_enable(CCGR_TSENSOR, 1);
 727         clock_enable(CCGR_OCOTP, 1);
 728
 729         /* config GIC ROOT to sys_pll2_200m */
 730         clock_enable(CCGR_GIC, 0);
 731         clock_set_target_val(GIC_CLK_ROOT,
 732                              CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
 733         clock_enable(CCGR_GIC, 1);
 734
 735         return 0;
 736 }
 737 #endif
 738
 739 /*
 740  * Dump some clockes.
 741  */
 742 #ifndef CONFIG_SPL_BUILD
 743 static int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
 744                        char * const argv[])
 745 {
 746         u32 freq;
 747
 748         freq = decode_frac_pll(ARM_PLL_CLK);
 749         printf("ARM_PLL    %8d MHz\n", freq / 1000000);
 750         freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
 751         printf("SYS_PLL1_800    %8d MHz\n", freq / 1000000);
 752         freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
 753         printf("SYS_PLL1_400    %8d MHz\n", freq / 1000000);
 754         freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
 755         printf("SYS_PLL1_266    %8d MHz\n", freq / 1000000);
 756         freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
 757         printf("SYS_PLL1_200    %8d MHz\n", freq / 1000000);
 758         freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
 759         printf("SYS_PLL1_160    %8d MHz\n", freq / 1000000);
 760         freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
 761         printf("SYS_PLL1_133    %8d MHz\n", freq / 1000000);
 762         freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
 763         printf("SYS_PLL1_100    %8d MHz\n", freq / 1000000);
 764         freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
 765         printf("SYS_PLL1_80    %8d MHz\n", freq / 1000000);
 766         freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
 767         printf("SYS_PLL1_40    %8d MHz\n", freq / 1000000);
 768         freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
 769         printf("SYS_PLL2_1000    %8d MHz\n", freq / 1000000);
 770         freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
 771         printf("SYS_PLL2_500    %8d MHz\n", freq / 1000000);
 772         freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
 773         printf("SYS_PLL2_333    %8d MHz\n", freq / 1000000);
 774         freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
 775         printf("SYS_PLL2_250    %8d MHz\n", freq / 1000000);
 776         freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
 777         printf("SYS_PLL2_200    %8d MHz\n", freq / 1000000);
 778         freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
 779         printf("SYS_PLL2_166    %8d MHz\n", freq / 1000000);
 780         freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
 781         printf("SYS_PLL2_125    %8d MHz\n", freq / 1000000);
 782         freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
 783         printf("SYS_PLL2_100    %8d MHz\n", freq / 1000000);
 784         freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
 785         printf("SYS_PLL2_50    %8d MHz\n", freq / 1000000);
 786         freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
 787         printf("SYS_PLL3       %8d MHz\n", freq / 1000000);
 788         freq = mxc_get_clock(UART1_CLK_ROOT);
 789         printf("UART1          %8d MHz\n", freq / 1000000);
 790         freq = mxc_get_clock(USDHC1_CLK_ROOT);
 791         printf("USDHC1         %8d MHz\n", freq / 1000000);
 792         freq = mxc_get_clock(QSPI_CLK_ROOT);
 793         printf("QSPI           %8d MHz\n", freq / 1000000);
 794         return 0;
 795 }
 796
 797 U_BOOT_CMD(
 798         clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,
 799         "display clocks",
 800         ""
 801 );
 802 #endif