arch/arm/mach-imx/imx8m/clock_imx8mq.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 NXP
   4  *
   5  * Peng Fan <peng.fan@nxp.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <errno.h>
  14 #include <linux/iopoll.h>
  15
  16 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  17
  18 static u32 decode_frac_pll(enum clk_root_src frac_pll)
  19 {
  20         u32 pll_cfg0, pll_cfg1, pllout;
  21         u32 pll_refclk_sel, pll_refclk;
  22         u32 divr_val, divq_val, divf_val, divff, divfi;
  23         u32 pllout_div_shift, pllout_div_mask, pllout_div;
  24
  25         switch (frac_pll) {
  26         case ARM_PLL_CLK:
  27                 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
  28                 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
  29                 pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
  30                 pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
  31                 break;
  32         default:
  33                 printf("Frac PLL %d not supporte\n", frac_pll);
  34                 return 0;
  35         }
  36
  37         pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
  38         pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
  39
  40         /* Power down */
  41         if (pll_cfg0 & FRAC_PLL_PD_MASK)
  42                 return 0;
  43
  44         /* output not enabled */
  45         if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
  46                 return 0;
  47
  48         pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
  49
  50         if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
  51                 pll_refclk = 25000000u;
  52         else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
  53                 pll_refclk = 27000000u;
  54         else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
  55                 pll_refclk = 27000000u;
  56         else
  57                 pll_refclk = 0;
  58
  59         if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
  60                 return pll_refclk;
  61
  62         divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
  63                 FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
  64         divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
  65
  66         divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
  67                 FRAC_PLL_FRAC_DIV_CTL_SHIFT;
  68         divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
  69
  70         divf_val = 1 + divfi + divff / (1 << 24);
  71
  72         pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
  73                 ((divq_val + 1) * 2);
  74
  75         return pllout / (pllout_div + 1);
  76 }
  77
  78 static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
  79 {
  80         u32 pll_cfg0, pll_cfg1, pll_cfg2;
  81         u32 pll_refclk_sel, pll_refclk;
  82         u32 divr1, divr2, divf1, divf2, divq, div;
  83         u32 sse;
  84         u32 pll_clke;
  85         u32 pllout_div_shift, pllout_div_mask, pllout_div;
  86         u32 pllout;
  87
  88         switch (sscg_pll) {
  89         case SYSTEM_PLL1_800M_CLK:
  90         case SYSTEM_PLL1_400M_CLK:
  91         case SYSTEM_PLL1_266M_CLK:
  92         case SYSTEM_PLL1_200M_CLK:
  93         case SYSTEM_PLL1_160M_CLK:
  94         case SYSTEM_PLL1_133M_CLK:
  95         case SYSTEM_PLL1_100M_CLK:
  96         case SYSTEM_PLL1_80M_CLK:
  97         case SYSTEM_PLL1_40M_CLK:
  98                 pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
  99                 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
 100                 pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
 101                 pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
 102                 pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
 103                 break;
 104         case SYSTEM_PLL2_1000M_CLK:
 105         case SYSTEM_PLL2_500M_CLK:
 106         case SYSTEM_PLL2_333M_CLK:
 107         case SYSTEM_PLL2_250M_CLK:
 108         case SYSTEM_PLL2_200M_CLK:
 109         case SYSTEM_PLL2_166M_CLK:
 110         case SYSTEM_PLL2_125M_CLK:
 111         case SYSTEM_PLL2_100M_CLK:
 112         case SYSTEM_PLL2_50M_CLK:
 113                 pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
 114                 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
 115                 pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
 116                 pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
 117                 pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
 118                 break;
 119         case SYSTEM_PLL3_CLK:
 120                 pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
 121                 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
 122                 pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
 123                 pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
 124                 pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
 125                 break;
 126         case DRAM_PLL1_CLK:
 127                 pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
 128                 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
 129                 pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
 130                 pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
 131                 pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
 132                 break;
 133         default:
 134                 printf("sscg pll %d not supporte\n", sscg_pll);
 135                 return 0;
 136         }
 137
 138         switch (sscg_pll) {
 139         case DRAM_PLL1_CLK:
 140                 pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
 141                 div = 1;
 142                 break;
 143         case SYSTEM_PLL3_CLK:
 144                 pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
 145                 div = 1;
 146                 break;
 147         case SYSTEM_PLL2_1000M_CLK:
 148         case SYSTEM_PLL1_800M_CLK:
 149                 pll_clke = SSCG_PLL_CLKE_MASK;
 150                 div = 1;
 151                 break;
 152         case SYSTEM_PLL2_500M_CLK:
 153         case SYSTEM_PLL1_400M_CLK:
 154                 pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
 155                 div = 2;
 156                 break;
 157         case SYSTEM_PLL2_333M_CLK:
 158         case SYSTEM_PLL1_266M_CLK:
 159                 pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
 160                 div = 3;
 161                 break;
 162         case SYSTEM_PLL2_250M_CLK:
 163         case SYSTEM_PLL1_200M_CLK:
 164                 pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
 165                 div = 4;
 166                 break;
 167         case SYSTEM_PLL2_200M_CLK:
 168         case SYSTEM_PLL1_160M_CLK:
 169                 pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
 170                 div = 5;
 171                 break;
 172         case SYSTEM_PLL2_166M_CLK:
 173         case SYSTEM_PLL1_133M_CLK:
 174                 pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
 175                 div = 6;
 176                 break;
 177         case SYSTEM_PLL2_125M_CLK:
 178         case SYSTEM_PLL1_100M_CLK:
 179                 pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
 180                 div = 8;
 181                 break;
 182         case SYSTEM_PLL2_100M_CLK:
 183         case SYSTEM_PLL1_80M_CLK:
 184                 pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
 185                 div = 10;
 186                 break;
 187         case SYSTEM_PLL2_50M_CLK:
 188         case SYSTEM_PLL1_40M_CLK:
 189                 pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
 190                 div = 20;
 191                 break;
 192         default:
 193                 printf("sscg pll %d not supporte\n", sscg_pll);
 194                 return 0;
 195         }
 196
 197         /* Power down */
 198         if (pll_cfg0 & SSCG_PLL_PD_MASK)
 199                 return 0;
 200
 201         /* output not enabled */
 202         if ((pll_cfg0 & pll_clke) == 0)
 203                 return 0;
 204
 205         pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
 206         pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
 207
 208         pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
 209
 210         if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
 211                 pll_refclk = 25000000u;
 212         else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
 213                 pll_refclk = 27000000u;
 214         else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
 215                 pll_refclk = 27000000u;
 216         else
 217                 pll_refclk = 0;
 218
 219         /* We assume bypass1/2 are the same value */
 220         if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
 221             (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
 222                 return pll_refclk;
 223
 224         divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
 225                 SSCG_PLL_REF_DIVR1_SHIFT;
 226         divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
 227                 SSCG_PLL_REF_DIVR2_SHIFT;
 228         divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
 229                 SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
 230         divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
 231                 SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
 232         divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
 233                 SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
 234         sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
 235
 236         if (sse)
 237                 sse = 8;
 238         else
 239                 sse = 2;
 240
 241         pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
 242                 (divr2 + 1) * (divf2 + 1) / (divq + 1);
 243
 244         return pllout / (pllout_div + 1) / div;
 245 }
 246
 247 static u32 get_root_src_clk(enum clk_root_src root_src)
 248 {
 249         switch (root_src) {
 250         case OSC_25M_CLK:
 251                 return 25000000;
 252         case OSC_27M_CLK:
 253                 return 27000000;
 254         case OSC_32K_CLK:
 255                 return 32768;
 256         case ARM_PLL_CLK:
 257                 return decode_frac_pll(root_src);
 258         case SYSTEM_PLL1_800M_CLK:
 259         case SYSTEM_PLL1_400M_CLK:
 260         case SYSTEM_PLL1_266M_CLK:
 261         case SYSTEM_PLL1_200M_CLK:
 262         case SYSTEM_PLL1_160M_CLK:
 263         case SYSTEM_PLL1_133M_CLK:
 264         case SYSTEM_PLL1_100M_CLK:
 265         case SYSTEM_PLL1_80M_CLK:
 266         case SYSTEM_PLL1_40M_CLK:
 267         case SYSTEM_PLL2_1000M_CLK:
 268         case SYSTEM_PLL2_500M_CLK:
 269         case SYSTEM_PLL2_333M_CLK:
 270         case SYSTEM_PLL2_250M_CLK:
 271         case SYSTEM_PLL2_200M_CLK:
 272         case SYSTEM_PLL2_166M_CLK:
 273         case SYSTEM_PLL2_125M_CLK:
 274         case SYSTEM_PLL2_100M_CLK:
 275         case SYSTEM_PLL2_50M_CLK:
 276         case SYSTEM_PLL3_CLK:
 277                 return decode_sscg_pll(root_src);
 278         default:
 279                 return 0;
 280         }
 281
 282         return 0;
 283 }
 284
 285 static u32 get_root_clk(enum clk_root_index clock_id)
 286 {
 287         enum clk_root_src root_src;
 288         u32 post_podf, pre_podf, root_src_clk;
 289
 290         if (clock_root_enabled(clock_id) <= 0)
 291                 return 0;
 292
 293         if (clock_get_prediv(clock_id, &pre_podf) < 0)
 294                 return 0;
 295
 296         if (clock_get_postdiv(clock_id, &post_podf) < 0)
 297                 return 0;
 298
 299         if (clock_get_src(clock_id, &root_src) < 0)
 300                 return 0;
 301
 302         root_src_clk = get_root_src_clk(root_src);
 303
 304         return root_src_clk / (post_podf + 1) / (pre_podf + 1);
 305 }
 306
 307 #ifdef CONFIG_MXC_OCOTP
 308 void enable_ocotp_clk(unsigned char enable)
 309 {
 310         clock_enable(CCGR_OCOTP, !!enable);
 311 }
 312 #endif
 313
 314 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
 315 {
 316         /* 0 - 3 is valid i2c num */
 317         if (i2c_num > 3)
 318                 return -EINVAL;
 319
 320         clock_enable(CCGR_I2C1 + i2c_num, !!enable);
 321
 322         return 0;
 323 }
 324
 325 unsigned int mxc_get_clock(enum mxc_clock clk)
 326 {
 327         u32 val;
 328
 329         if (clk == MXC_ARM_CLK)
 330                 return get_root_clk(ARM_A53_CLK_ROOT);
 331
 332         if (clk == MXC_IPG_CLK) {
 333                 clock_get_target_val(IPG_CLK_ROOT, &val);
 334                 val = val & 0x3;
 335                 return get_root_clk(AHB_CLK_ROOT) / (val + 1);
 336         }
 337
 338         return get_root_clk(clk);
 339 }
 340
 341 u32 imx_get_uartclk(void)
 342 {
 343         return mxc_get_clock(UART1_CLK_ROOT);
 344 }
 345
 346 void mxs_set_lcdclk(u32 base_addr, u32 freq)
 347 {
 348         /*
 349          * LCDIF_PIXEL_CLK: select 800MHz root clock,
 350          * select pre divider 8, output is 100 MHz
 351          */
 352         clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
 353                              CLK_ROOT_SOURCE_SEL(4) |
 354                              CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
 355 }
 356
 357 void init_wdog_clk(void)
 358 {
 359         clock_enable(CCGR_WDOG1, 0);
 360         clock_enable(CCGR_WDOG2, 0);
 361         clock_enable(CCGR_WDOG3, 0);
 362         clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
 363                              CLK_ROOT_SOURCE_SEL(0));
 364         clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
 365                              CLK_ROOT_SOURCE_SEL(0));
 366         clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
 367                              CLK_ROOT_SOURCE_SEL(0));
 368         clock_enable(CCGR_WDOG1, 1);
 369         clock_enable(CCGR_WDOG2, 1);
 370         clock_enable(CCGR_WDOG3, 1);
 371 }
 372
 373 void init_usb_clk(void)
 374 {
 375         if (!is_usb_boot()) {
 376                 clock_enable(CCGR_USB_CTRL1, 0);
 377                 clock_enable(CCGR_USB_CTRL2, 0);
 378                 clock_enable(CCGR_USB_PHY1, 0);
 379                 clock_enable(CCGR_USB_PHY2, 0);
 380                 /* 500MHz */
 381                 clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
 382                                      CLK_ROOT_SOURCE_SEL(1));
 383                 /* 100MHz */
 384                 clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
 385                                      CLK_ROOT_SOURCE_SEL(1));
 386                 /* 100MHz */
 387                 clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
 388                                      CLK_ROOT_SOURCE_SEL(1));
 389                 clock_enable(CCGR_USB_CTRL1, 1);
 390                 clock_enable(CCGR_USB_CTRL2, 1);
 391                 clock_enable(CCGR_USB_PHY1, 1);
 392                 clock_enable(CCGR_USB_PHY2, 1);
 393         }
 394 }
 395
 396 void init_uart_clk(u32 index)
 397 {
 398         /* Set uart clock root 25M OSC */
 399         switch (index) {
 400         case 0:
 401                 clock_enable(CCGR_UART1, 0);
 402                 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
 403                                      CLK_ROOT_SOURCE_SEL(0));
 404                 clock_enable(CCGR_UART1, 1);
 405                 return;
 406         case 1:
 407                 clock_enable(CCGR_UART2, 0);
 408                 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
 409                                      CLK_ROOT_SOURCE_SEL(0));
 410                 clock_enable(CCGR_UART2, 1);
 411                 return;
 412         case 2:
 413                 clock_enable(CCGR_UART3, 0);
 414                 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
 415                                      CLK_ROOT_SOURCE_SEL(0));
 416                 clock_enable(CCGR_UART3, 1);
 417                 return;
 418         case 3:
 419                 clock_enable(CCGR_UART4, 0);
 420                 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
 421                                      CLK_ROOT_SOURCE_SEL(0));
 422                 clock_enable(CCGR_UART4, 1);
 423                 return;
 424         default:
 425                 printf("Invalid uart index\n");
 426                 return;
 427         }
 428 }
 429
 430 void init_clk_usdhc(u32 index)
 431 {
 432         /*
 433          * set usdhc clock root
 434          * sys pll1 400M
 435          */
 436         switch (index) {
 437         case 0:
 438                 clock_enable(CCGR_USDHC1, 0);
 439                 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
 440                                      CLK_ROOT_SOURCE_SEL(1) |
 441                                      CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
 442                 clock_enable(CCGR_USDHC1, 1);
 443                 return;
 444         case 1:
 445                 clock_enable(CCGR_USDHC2, 0);
 446                 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
 447                                      CLK_ROOT_SOURCE_SEL(1) |
 448                                      CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
 449                 clock_enable(CCGR_USDHC2, 1);
 450                 return;
 451         default:
 452                 printf("Invalid usdhc index\n");
 453                 return;
 454         }
 455 }
 456
 457 int set_clk_qspi(void)
 458 {
 459         /*
 460          * set qspi root
 461          * sys pll1 100M
 462          */
 463         clock_enable(CCGR_QSPI, 0);
 464         clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
 465                              CLK_ROOT_SOURCE_SEL(7));
 466         clock_enable(CCGR_QSPI, 1);
 467
 468         return 0;
 469 }
 470
 471 #ifdef CONFIG_FEC_MXC
 472 int set_clk_enet(enum enet_freq type)
 473 {
 474         u32 target;
 475         u32 enet1_ref;
 476
 477         switch (type) {
 478         case ENET_125MHZ:
 479                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
 480                 break;
 481         case ENET_50MHZ:
 482                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
 483                 break;
 484         case ENET_25MHZ:
 485                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
 486                 break;
 487         default:
 488                 return -EINVAL;
 489         }
 490
 491         /* disable the clock first */
 492         clock_enable(CCGR_ENET1, 0);
 493         clock_enable(CCGR_SIM_ENET, 0);
 494
 495         /* set enet axi clock 266Mhz */
 496         target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
 497                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 498                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 499         clock_set_target_val(ENET_AXI_CLK_ROOT, target);
 500
 501         target = CLK_ROOT_ON | enet1_ref |
 502                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 503                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 504         clock_set_target_val(ENET_REF_CLK_ROOT, target);
 505
 506         target = CLK_ROOT_ON |
 507                 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
 508                 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 509                 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
 510         clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
 511
 512         /* enable clock */
 513         clock_enable(CCGR_SIM_ENET, 1);
 514         clock_enable(CCGR_ENET1, 1);
 515
 516         return 0;
 517 }
 518 #endif
 519
 520 u32 imx_get_fecclk(void)
 521 {
 522         return get_root_clk(ENET_AXI_CLK_ROOT);
 523 }
 524
 525 static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
 526         DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
 527                                 CLK_ROOT_PRE_DIV2),
 528         DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
 529                                 CLK_ROOT_PRE_DIV2),
 530         DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
 531                                 CLK_ROOT_PRE_DIV2),
 532 };
 533
 534 void dram_enable_bypass(ulong clk_val)
 535 {
 536         int i;
 537         struct dram_bypass_clk_setting *config;
 538
 539         for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
 540                 if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
 541                         break;
 542         }
 543
 544         if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
 545                 printf("No matched freq table %lu\n", clk_val);
 546                 return;
 547         }
 548
 549         config = &imx8mq_dram_bypass_tbl[i];
 550
 551         clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
 552                              CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
 553                              CLK_ROOT_PRE_DIV(config->alt_pre_div));
 554         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 555                              CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
 556                              CLK_ROOT_PRE_DIV(config->apb_pre_div));
 557         clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
 558                              CLK_ROOT_SOURCE_SEL(1));
 559 }
 560
 561 void dram_disable_bypass(void)
 562 {
 563         clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
 564                              CLK_ROOT_SOURCE_SEL(0));
 565         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
 566                              CLK_ROOT_SOURCE_SEL(4) |
 567                              CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
 568 }
 569
 570 #ifdef CONFIG_SPL_BUILD
 571 void dram_pll_init(ulong pll_val)
 572 {
 573         u32 val;
 574         void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
 575         void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
 576
 577         /* Bypass */
 578         setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
 579         setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
 580
 581         switch (pll_val) {
 582         case MHZ(800):
 583                 val = readl(pll_cfg_reg2);
 584                 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
 585                          SSCG_PLL_FEEDBACK_DIV_F2_MASK |
 586                          SSCG_PLL_FEEDBACK_DIV_F1_MASK |
 587                          SSCG_PLL_REF_DIVR2_MASK);
 588                 val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
 589                 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
 590                 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
 591                 val |= SSCG_PLL_REF_DIVR2_VAL(29);
 592                 writel(val, pll_cfg_reg2);
 593                 break;
 594         case MHZ(600):
 595                 val = readl(pll_cfg_reg2);
 596                 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
 597                          SSCG_PLL_FEEDBACK_DIV_F2_MASK |
 598                          SSCG_PLL_FEEDBACK_DIV_F1_MASK |
 599                          SSCG_PLL_REF_DIVR2_MASK);
 600                 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
 601                 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
 602                 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
 603                 val |= SSCG_PLL_REF_DIVR2_VAL(29);
 604                 writel(val, pll_cfg_reg2);
 605                 break;
 606         case MHZ(400):
 607                 val = readl(pll_cfg_reg2);
 608                 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
 609                          SSCG_PLL_FEEDBACK_DIV_F2_MASK |
 610                          SSCG_PLL_FEEDBACK_DIV_F1_MASK |
 611                          SSCG_PLL_REF_DIVR2_MASK);
 612                 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
 613                 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
 614                 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
 615                 val |= SSCG_PLL_REF_DIVR2_VAL(29);
 616                 writel(val, pll_cfg_reg2);
 617                 break;
 618         case MHZ(167):
 619                 val = readl(pll_cfg_reg2);
 620                 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
 621                          SSCG_PLL_FEEDBACK_DIV_F2_MASK |
 622                          SSCG_PLL_FEEDBACK_DIV_F1_MASK |
 623                          SSCG_PLL_REF_DIVR2_MASK);
 624                 val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
 625                 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
 626                 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
 627                 val |= SSCG_PLL_REF_DIVR2_VAL(30);
 628                 writel(val, pll_cfg_reg2);
 629                 break;
 630         default:
 631                 break;
 632         }
 633
 634         /* Clear power down bit */
 635         clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
 636         /* Eanble ARM_PLL/SYS_PLL  */
 637         setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
 638
 639         /* Clear bypass */
 640         clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
 641         __udelay(100);
 642         clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
 643         /* Wait lock */
 644         while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
 645                 ;
 646 }
 647
 648 int frac_pll_init(u32 pll, enum frac_pll_out_val val)
 649 {
 650         void __iomem *pll_cfg0, __iomem *pll_cfg1;
 651         u32 val_cfg0, val_cfg1;
 652         int ret;
 653
 654         switch (pll) {
 655         case ANATOP_ARM_PLL:
 656                 pll_cfg0 = &ana_pll->arm_pll_cfg0;
 657                 pll_cfg1 = &ana_pll->arm_pll_cfg1;
 658
 659                 if (val == FRAC_PLL_OUT_1000M)
 660                         val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
 661                 else
 662                         val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
 663                 val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
 664                         FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
 665                         FRAC_PLL_REFCLK_DIV_VAL(4) |
 666                         FRAC_PLL_OUTPUT_DIV_VAL(0);
 667                 break;
 668         default:
 669                 return -EINVAL;
 670         }
 671
 672         /* bypass the clock */
 673         setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
 674         /* Set the value */
 675         writel(val_cfg1, pll_cfg1);
 676         writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
 677         val_cfg0 = readl(pll_cfg0);
 678         /* unbypass the clock */
 679         clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
 680         ret = readl_poll_timeout(pll_cfg0, val_cfg0,
 681                                  val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
 682         if (ret)
 683                 printf("%s timeout\n", __func__);
 684         clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
 685
 686         return 0;
 687 }
 688
 689 int sscg_pll_init(u32 pll)
 690 {
 691         void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;
 692         u32 val_cfg0, val_cfg1, val_cfg2, val;
 693         u32 bypass1_mask = 0x20, bypass2_mask = 0x10;
 694         int ret;
 695
 696         switch (pll) {
 697         case ANATOP_SYSTEM_PLL1:
 698                 pll_cfg0 = &ana_pll->sys_pll1_cfg0;
 699                 pll_cfg1 = &ana_pll->sys_pll1_cfg1;
 700                 pll_cfg2 = &ana_pll->sys_pll1_cfg2;
 701                 /* 800MHz */
 702                 val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
 703                         SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
 704                 val_cfg1 = 0;
 705                 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
 706                         SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
 707                         SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
 708                         SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
 709                         SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
 710                         SSCG_PLL_REFCLK_SEL_OSC_25M;
 711                 break;
 712         case ANATOP_SYSTEM_PLL2:
 713                 pll_cfg0 = &ana_pll->sys_pll2_cfg0;
 714                 pll_cfg1 = &ana_pll->sys_pll2_cfg1;
 715                 pll_cfg2 = &ana_pll->sys_pll2_cfg2;
 716                 /* 1000MHz */
 717                 val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
 718                         SSCG_PLL_FEEDBACK_DIV_F2_VAL(4);
 719                 val_cfg1 = 0;
 720                 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
 721                         SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
 722                         SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
 723                         SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
 724                         SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
 725                         SSCG_PLL_REFCLK_SEL_OSC_25M;
 726                 break;
 727         case ANATOP_SYSTEM_PLL3:
 728                 pll_cfg0 = &ana_pll->sys_pll3_cfg0;
 729                 pll_cfg1 = &ana_pll->sys_pll3_cfg1;
 730                 pll_cfg2 = &ana_pll->sys_pll3_cfg2;
 731                 /* 800MHz */
 732                 val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
 733                         SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
 734                 val_cfg1 = 0;
 735                 val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK |  SSCG_PLL_LOCK_SEL_MASK |
 736                         SSCG_PLL_REFCLK_SEL_OSC_25M;
 737                 break;
 738         default:
 739                 return -EINVAL;
 740         }
 741
 742         /*bypass*/
 743         setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);
 744         /* set value */
 745         writel(val_cfg2, pll_cfg2);
 746         writel(val_cfg1, pll_cfg1);
 747         /*unbypass1 and wait 70us */
 748         writel(val_cfg0 | bypass2_mask, pll_cfg1);
 749
 750         __udelay(70);
 751
 752         /* unbypass2 and wait lock */
 753         writel(val_cfg0, pll_cfg1);
 754         ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1);
 755         if (ret)
 756                 printf("%s timeout\n", __func__);
 757
 758         return ret;
 759 }
 760
 761 int clock_init(void)
 762 {
 763         u32 grade;
 764
 765         clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
 766                              CLK_ROOT_SOURCE_SEL(0));
 767
 768         /*
 769          * 8MQ only supports two grades: consumer and industrial.
 770          * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
 771          */
 772         grade = get_cpu_temp_grade(NULL, NULL);
 773         if (!grade) {
 774                 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
 775                 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
 776                              CLK_ROOT_SOURCE_SEL(1) |
 777                              CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
 778         } else {
 779                 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M);
 780                 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
 781                              CLK_ROOT_SOURCE_SEL(1) |
 782                              CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
 783         }
 784         /*
 785          * According to ANAMIX SPEC
 786          * sys pll1 fixed at 800MHz
 787          * sys pll2 fixed at 1GHz
 788          * Here we only enable the outputs.
 789          */
 790         setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
 791                      SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
 792                      SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
 793                      SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
 794                      SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
 795
 796         setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
 797                      SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
 798                      SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
 799                      SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
 800                      SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
 801
 802         clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
 803                              CLK_ROOT_SOURCE_SEL(1));
 804
 805         init_wdog_clk();
 806         clock_enable(CCGR_TSENSOR, 1);
 807         clock_enable(CCGR_OCOTP, 1);
 808
 809         /* config GIC ROOT to sys_pll2_200m */
 810         clock_enable(CCGR_GIC, 0);
 811         clock_set_target_val(GIC_CLK_ROOT,
 812                              CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
 813         clock_enable(CCGR_GIC, 1);
 814
 815         return 0;
 816 }
 817 #endif
 818
 819 /*
 820  * Dump some clockes.
 821  */
 822 #ifndef CONFIG_SPL_BUILD
 823 int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
 824                        char * const argv[])
 825 {
 826         u32 freq;
 827
 828         freq = decode_frac_pll(ARM_PLL_CLK);
 829         printf("ARM_PLL    %8d MHz\n", freq / 1000000);
 830         freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
 831         printf("SYS_PLL1_800    %8d MHz\n", freq / 1000000);
 832         freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
 833         printf("SYS_PLL1_400    %8d MHz\n", freq / 1000000);
 834         freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
 835         printf("SYS_PLL1_266    %8d MHz\n", freq / 1000000);
 836         freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
 837         printf("SYS_PLL1_200    %8d MHz\n", freq / 1000000);
 838         freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
 839         printf("SYS_PLL1_160    %8d MHz\n", freq / 1000000);
 840         freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
 841         printf("SYS_PLL1_133    %8d MHz\n", freq / 1000000);
 842         freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
 843         printf("SYS_PLL1_100    %8d MHz\n", freq / 1000000);
 844         freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
 845         printf("SYS_PLL1_80    %8d MHz\n", freq / 1000000);
 846         freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
 847         printf("SYS_PLL1_40    %8d MHz\n", freq / 1000000);
 848         freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
 849         printf("SYS_PLL2_1000    %8d MHz\n", freq / 1000000);
 850         freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
 851         printf("SYS_PLL2_500    %8d MHz\n", freq / 1000000);
 852         freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
 853         printf("SYS_PLL2_333    %8d MHz\n", freq / 1000000);
 854         freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
 855         printf("SYS_PLL2_250    %8d MHz\n", freq / 1000000);
 856         freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
 857         printf("SYS_PLL2_200    %8d MHz\n", freq / 1000000);
 858         freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
 859         printf("SYS_PLL2_166    %8d MHz\n", freq / 1000000);
 860         freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
 861         printf("SYS_PLL2_125    %8d MHz\n", freq / 1000000);
 862         freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
 863         printf("SYS_PLL2_100    %8d MHz\n", freq / 1000000);
 864         freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
 865         printf("SYS_PLL2_50    %8d MHz\n", freq / 1000000);
 866         freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
 867         printf("SYS_PLL3       %8d MHz\n", freq / 1000000);
 868         freq = mxc_get_clock(UART1_CLK_ROOT);
 869         printf("UART1          %8d MHz\n", freq / 1000000);
 870         freq = mxc_get_clock(USDHC1_CLK_ROOT);
 871         printf("USDHC1         %8d MHz\n", freq / 1000000);
 872         freq = mxc_get_clock(QSPI_CLK_ROOT);
 873         printf("QSPI           %8d MHz\n", freq / 1000000);
 874         return 0;
 875 }
 876
 877 U_BOOT_CMD(
 878         clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,
 879         "display clocks",
 880         ""
 881 );
 882 #endif