1 // SPDX-License-Identifier: GPL-2.0+
10 #include <dm/device-internal.h>
12 #include <dm/uclass.h>
14 #include <asm/arch/sci/sci.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/arch-imx/cpu.h>
17 #include <asm/armv8/cpu.h>
18 #include <asm/armv8/mmu.h>
19 #include <asm/mach-imx/boot_mode.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 #define BT_PASSOVER_TAG 0x504F
24 struct pass_over_info_t *get_pass_over_info(void)
26 struct pass_over_info_t *p =
27 (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
29 if (p->barker != BT_PASSOVER_TAG ||
30 p->len != sizeof(struct pass_over_info_t))
36 int arch_cpu_init(void)
38 struct pass_over_info_t *pass_over = get_pass_over_info();
40 if (pass_over && pass_over->g_ap_mu == 0) {
42 * When ap_mu is 0, means the U-Boot booted
43 * from first container
45 sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
51 int arch_cpu_init_dm(void)
56 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
57 ret = device_bind_driver_to_node(gd->dm_root, "imx8_scu", "imx8_scu",
58 offset_to_ofnode(node), &devp);
61 printf("could not find scu %d\n", ret);
65 ret = device_probe(devp);
67 printf("scu probe failed %d\n", ret);
74 int print_bootinfo(void)
76 enum boot_device bt_dev = get_boot_device();
111 printf("Unknown device %u\n", bt_dev);
118 enum boot_device get_boot_device(void)
120 enum boot_device boot_dev = SD1_BOOT;
124 sc_misc_get_boot_dev(-1, &dev_rsrc);
128 boot_dev = MMC1_BOOT;
137 boot_dev = NAND_BOOT;
140 boot_dev = FLEXSPI_BOOT;
143 boot_dev = SATA_BOOT;
157 #ifdef CONFIG_ENV_IS_IN_MMC
158 __weak int board_mmc_get_env_dev(int devno)
160 return CONFIG_SYS_MMC_ENV_DEV;
163 int mmc_get_env_dev(void)
168 sc_misc_get_boot_dev(-1, &dev_rsrc);
181 /* If not boot from sd/mmc, use default value */
182 return CONFIG_SYS_MMC_ENV_DEV;
185 return board_mmc_get_env_dev(devno);
189 #define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */
191 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
192 sc_faddr_t *addr_end)
194 sc_faddr_t start, end;
198 owned = sc_rm_is_memreg_owned(-1, mr);
200 ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
202 printf("Memreg get info failed, %d\n", ret);
205 debug("0x%llx -- 0x%llx\n", start, end);
215 phys_size_t get_effective_memsize(void)
218 sc_faddr_t start, end, end1;
221 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
223 for (mr = 0; mr < 64; mr++) {
224 err = get_owned_memreg(mr, &start, &end);
226 start = roundup(start, MEMSTART_ALIGNMENT);
227 /* Too small memory region, not use it */
231 /* Find the memory region runs the U-Boot */
232 if (start >= PHYS_SDRAM_1 && start <= end1 &&
233 (start <= CONFIG_SYS_TEXT_BASE &&
234 end >= CONFIG_SYS_TEXT_BASE)) {
235 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
237 return (end - PHYS_SDRAM_1 + 1);
239 return PHYS_SDRAM_1_SIZE;
244 return PHYS_SDRAM_1_SIZE;
250 sc_faddr_t start, end, end1, end2;
253 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
254 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
255 for (mr = 0; mr < 64; mr++) {
256 err = get_owned_memreg(mr, &start, &end);
258 start = roundup(start, MEMSTART_ALIGNMENT);
259 /* Too small memory region, not use it */
263 if (start >= PHYS_SDRAM_1 && start <= end1) {
264 if ((end + 1) <= end1)
265 gd->ram_size += end - start + 1;
267 gd->ram_size += end1 - start;
268 } else if (start >= PHYS_SDRAM_2 && start <= end2) {
269 if ((end + 1) <= end2)
270 gd->ram_size += end - start + 1;
272 gd->ram_size += end2 - start;
277 /* If error, set to the default value */
279 gd->ram_size = PHYS_SDRAM_1_SIZE;
280 gd->ram_size += PHYS_SDRAM_2_SIZE;
285 static void dram_bank_sort(int current_bank)
290 while (current_bank > 0) {
291 if (gd->bd->bi_dram[current_bank - 1].start >
292 gd->bd->bi_dram[current_bank].start) {
293 start = gd->bd->bi_dram[current_bank - 1].start;
294 size = gd->bd->bi_dram[current_bank - 1].size;
296 gd->bd->bi_dram[current_bank - 1].start =
297 gd->bd->bi_dram[current_bank].start;
298 gd->bd->bi_dram[current_bank - 1].size =
299 gd->bd->bi_dram[current_bank].size;
301 gd->bd->bi_dram[current_bank].start = start;
302 gd->bd->bi_dram[current_bank].size = size;
308 int dram_init_banksize(void)
311 sc_faddr_t start, end, end1, end2;
315 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
316 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
318 for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
319 err = get_owned_memreg(mr, &start, &end);
321 start = roundup(start, MEMSTART_ALIGNMENT);
322 if (start > end) /* Small memory region, no use it */
325 if (start >= PHYS_SDRAM_1 && start <= end1) {
326 gd->bd->bi_dram[i].start = start;
328 if ((end + 1) <= end1)
329 gd->bd->bi_dram[i].size =
332 gd->bd->bi_dram[i].size = end1 - start;
336 } else if (start >= PHYS_SDRAM_2 && start <= end2) {
337 gd->bd->bi_dram[i].start = start;
339 if ((end + 1) <= end2)
340 gd->bd->bi_dram[i].size =
343 gd->bd->bi_dram[i].size = end2 - start;
351 /* If error, set to the default value */
353 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
354 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
355 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
356 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
362 static u64 get_block_attrs(sc_faddr_t addr_start)
364 u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
365 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
367 if ((addr_start >= PHYS_SDRAM_1 &&
368 addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
369 (addr_start >= PHYS_SDRAM_2 &&
370 addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
371 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
376 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
378 sc_faddr_t end1, end2;
380 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
381 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
383 if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
384 if ((addr_end + 1) > end1)
385 return end1 - addr_start;
386 } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
387 if ((addr_end + 1) > end2)
388 return end2 - addr_start;
391 return (addr_end - addr_start + 1);
394 #define MAX_PTE_ENTRIES 512
395 #define MAX_MEM_MAP_REGIONS 16
397 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
398 struct mm_region *mem_map = imx8_mem_map;
400 void enable_caches(void)
403 sc_faddr_t start, end;
406 /* Create map for registers access from 0x1c000000 to 0x80000000*/
407 imx8_mem_map[0].virt = 0x1c000000UL;
408 imx8_mem_map[0].phys = 0x1c000000UL;
409 imx8_mem_map[0].size = 0x64000000UL;
410 imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
411 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
414 for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
415 err = get_owned_memreg(mr, &start, &end);
417 imx8_mem_map[i].virt = start;
418 imx8_mem_map[i].phys = start;
419 imx8_mem_map[i].size = get_block_size(start, end);
420 imx8_mem_map[i].attrs = get_block_attrs(start);
425 if (i < MAX_MEM_MAP_REGIONS) {
426 imx8_mem_map[i].size = 0;
427 imx8_mem_map[i].attrs = 0;
429 puts("Error, need more MEM MAP REGIONS reserved\n");
434 for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
435 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
436 i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
437 imx8_mem_map[i].size, imx8_mem_map[i].attrs);
444 #ifndef CONFIG_SYS_DCACHE_OFF
445 u64 get_page_table_size(void)
447 u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
451 * For each memory region, the max table size:
452 * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
454 size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
457 * We need to duplicate our page table once to have an emergency pt to
458 * resort to when splitting page tables later on
463 * We may need to split page tables later on if dcache settings change,
464 * so reserve up to 4 (random pick) page tables for that.
472 #define FUSE_MAC0_WORD0 708
473 #define FUSE_MAC0_WORD1 709
474 #define FUSE_MAC1_WORD0 710
475 #define FUSE_MAC1_WORD1 711
477 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
479 u32 word[2], val[2] = {};
483 word[0] = FUSE_MAC0_WORD0;
484 word[1] = FUSE_MAC0_WORD1;
486 word[0] = FUSE_MAC1_WORD0;
487 word[1] = FUSE_MAC1_WORD1;
490 for (i = 0; i < 2; i++) {
491 ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
497 mac[1] = val[0] >> 8;
498 mac[2] = val[0] >> 16;
499 mac[3] = val[0] >> 24;
501 mac[5] = val[1] >> 8;
503 debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
504 __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
507 printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
510 #if CONFIG_IS_ENABLED(CPU)
511 struct cpu_imx_platdata {
519 u32 get_cpu_rev(void)
524 ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
528 rev = (id >> 5) & 0xf;
529 id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
531 return (id << 12) | rev;
534 const char *get_imx8_type(u32 imxtype)
537 case MXC_CPU_IMX8QXP:
538 case MXC_CPU_IMX8QXP_A0:
545 const char *get_imx8_rev(u32 rev)
557 const char *get_core_name(void)
561 else if (is_cortex_a53())
563 else if (is_cortex_a72())
569 int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)
571 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
576 snprintf(buf, size, "CPU: Freescale i.MX8%s Rev%s %s at %u MHz\n",
577 plat->type, plat->rev, plat->name, plat->freq_mhz);
582 static int cpu_imx_get_info(struct udevice *dev, struct cpu_info *info)
584 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
586 info->cpu_freq = plat->freq_mhz * 1000;
587 info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
591 static int cpu_imx_get_count(struct udevice *dev)
596 static int cpu_imx_get_vendor(struct udevice *dev, char *buf, int size)
598 snprintf(buf, size, "NXP");
602 static const struct cpu_ops cpu_imx8_ops = {
603 .get_desc = cpu_imx_get_desc,
604 .get_info = cpu_imx_get_info,
605 .get_count = cpu_imx_get_count,
606 .get_vendor = cpu_imx_get_vendor,
609 static const struct udevice_id cpu_imx8_ids[] = {
610 { .compatible = "arm,cortex-a35" },
614 static int imx8_cpu_probe(struct udevice *dev)
616 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
621 cpurev = get_cpu_rev();
622 plat->cpurev = cpurev;
623 plat->name = get_core_name();
624 plat->rev = get_imx8_rev(cpurev & 0xFFF);
625 plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);
627 ret = clk_get_by_index(dev, 0, &cpu_clk);
629 debug("%s: Failed to get CPU clk: %d\n", __func__, ret);
633 plat->freq_mhz = clk_get_rate(&cpu_clk) / 1000000;
637 U_BOOT_DRIVER(cpu_imx8_drv) = {
640 .of_match = cpu_imx8_ids,
641 .ops = &cpu_imx8_ops,
642 .probe = imx8_cpu_probe,
643 .platdata_auto_alloc_size = sizeof(struct cpu_imx_platdata),
644 .flags = DM_FLAG_PRE_RELOC,