1 // SPDX-License-Identifier: GPL-2.0+
11 #include <dm/device-internal.h>
13 #include <dm/uclass.h>
16 #include <asm/arch/sci/sci.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch-imx/cpu.h>
19 #include <asm/armv8/cpu.h>
20 #include <asm/armv8/mmu.h>
21 #include <asm/mach-imx/boot_mode.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #define BT_PASSOVER_TAG 0x504F
26 struct pass_over_info_t *get_pass_over_info(void)
28 struct pass_over_info_t *p =
29 (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
31 if (p->barker != BT_PASSOVER_TAG ||
32 p->len != sizeof(struct pass_over_info_t))
38 int arch_cpu_init(void)
40 #ifdef CONFIG_SPL_BUILD
41 struct pass_over_info_t *pass_over;
43 if (is_soc_rev(CHIP_REV_A)) {
44 pass_over = get_pass_over_info();
45 if (pass_over && pass_over->g_ap_mu == 0) {
47 * When ap_mu is 0, means the U-Boot booted
48 * from first container
50 sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
58 int arch_cpu_init_dm(void)
63 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
65 ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
67 printf("could not get scu %d\n", ret);
72 ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
81 int print_bootinfo(void)
83 enum boot_device bt_dev = get_boot_device();
118 printf("Unknown device %u\n", bt_dev);
125 enum boot_device get_boot_device(void)
127 enum boot_device boot_dev = SD1_BOOT;
131 sc_misc_get_boot_dev(-1, &dev_rsrc);
135 boot_dev = MMC1_BOOT;
144 boot_dev = NAND_BOOT;
147 boot_dev = FLEXSPI_BOOT;
150 boot_dev = SATA_BOOT;
164 #ifdef CONFIG_ENV_IS_IN_MMC
165 __weak int board_mmc_get_env_dev(int devno)
167 return CONFIG_SYS_MMC_ENV_DEV;
170 int mmc_get_env_dev(void)
175 sc_misc_get_boot_dev(-1, &dev_rsrc);
188 /* If not boot from sd/mmc, use default value */
189 return CONFIG_SYS_MMC_ENV_DEV;
192 return board_mmc_get_env_dev(devno);
196 #define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */
198 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
199 sc_faddr_t *addr_end)
201 sc_faddr_t start, end;
205 owned = sc_rm_is_memreg_owned(-1, mr);
207 ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
209 printf("Memreg get info failed, %d\n", ret);
212 debug("0x%llx -- 0x%llx\n", start, end);
222 phys_size_t get_effective_memsize(void)
225 sc_faddr_t start, end, end1;
228 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
230 for (mr = 0; mr < 64; mr++) {
231 err = get_owned_memreg(mr, &start, &end);
233 start = roundup(start, MEMSTART_ALIGNMENT);
234 /* Too small memory region, not use it */
238 /* Find the memory region runs the U-Boot */
239 if (start >= PHYS_SDRAM_1 && start <= end1 &&
240 (start <= CONFIG_SYS_TEXT_BASE &&
241 end >= CONFIG_SYS_TEXT_BASE)) {
242 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
244 return (end - PHYS_SDRAM_1 + 1);
246 return PHYS_SDRAM_1_SIZE;
251 return PHYS_SDRAM_1_SIZE;
257 sc_faddr_t start, end, end1, end2;
260 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
261 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
262 for (mr = 0; mr < 64; mr++) {
263 err = get_owned_memreg(mr, &start, &end);
265 start = roundup(start, MEMSTART_ALIGNMENT);
266 /* Too small memory region, not use it */
270 if (start >= PHYS_SDRAM_1 && start <= end1) {
271 if ((end + 1) <= end1)
272 gd->ram_size += end - start + 1;
274 gd->ram_size += end1 - start;
275 } else if (start >= PHYS_SDRAM_2 && start <= end2) {
276 if ((end + 1) <= end2)
277 gd->ram_size += end - start + 1;
279 gd->ram_size += end2 - start;
284 /* If error, set to the default value */
286 gd->ram_size = PHYS_SDRAM_1_SIZE;
287 gd->ram_size += PHYS_SDRAM_2_SIZE;
292 static void dram_bank_sort(int current_bank)
297 while (current_bank > 0) {
298 if (gd->bd->bi_dram[current_bank - 1].start >
299 gd->bd->bi_dram[current_bank].start) {
300 start = gd->bd->bi_dram[current_bank - 1].start;
301 size = gd->bd->bi_dram[current_bank - 1].size;
303 gd->bd->bi_dram[current_bank - 1].start =
304 gd->bd->bi_dram[current_bank].start;
305 gd->bd->bi_dram[current_bank - 1].size =
306 gd->bd->bi_dram[current_bank].size;
308 gd->bd->bi_dram[current_bank].start = start;
309 gd->bd->bi_dram[current_bank].size = size;
315 int dram_init_banksize(void)
318 sc_faddr_t start, end, end1, end2;
322 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
323 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
325 for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
326 err = get_owned_memreg(mr, &start, &end);
328 start = roundup(start, MEMSTART_ALIGNMENT);
329 if (start > end) /* Small memory region, no use it */
332 if (start >= PHYS_SDRAM_1 && start <= end1) {
333 gd->bd->bi_dram[i].start = start;
335 if ((end + 1) <= end1)
336 gd->bd->bi_dram[i].size =
339 gd->bd->bi_dram[i].size = end1 - start;
343 } else if (start >= PHYS_SDRAM_2 && start <= end2) {
344 gd->bd->bi_dram[i].start = start;
346 if ((end + 1) <= end2)
347 gd->bd->bi_dram[i].size =
350 gd->bd->bi_dram[i].size = end2 - start;
358 /* If error, set to the default value */
360 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
361 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
362 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
363 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
369 static u64 get_block_attrs(sc_faddr_t addr_start)
371 u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
372 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
374 if ((addr_start >= PHYS_SDRAM_1 &&
375 addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
376 (addr_start >= PHYS_SDRAM_2 &&
377 addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
378 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
383 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
385 sc_faddr_t end1, end2;
387 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
388 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
390 if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
391 if ((addr_end + 1) > end1)
392 return end1 - addr_start;
393 } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
394 if ((addr_end + 1) > end2)
395 return end2 - addr_start;
398 return (addr_end - addr_start + 1);
401 #define MAX_PTE_ENTRIES 512
402 #define MAX_MEM_MAP_REGIONS 16
404 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
405 struct mm_region *mem_map = imx8_mem_map;
407 void enable_caches(void)
410 sc_faddr_t start, end;
413 /* Create map for registers access from 0x1c000000 to 0x80000000*/
414 imx8_mem_map[0].virt = 0x1c000000UL;
415 imx8_mem_map[0].phys = 0x1c000000UL;
416 imx8_mem_map[0].size = 0x64000000UL;
417 imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
418 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
421 for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
422 err = get_owned_memreg(mr, &start, &end);
424 imx8_mem_map[i].virt = start;
425 imx8_mem_map[i].phys = start;
426 imx8_mem_map[i].size = get_block_size(start, end);
427 imx8_mem_map[i].attrs = get_block_attrs(start);
432 if (i < MAX_MEM_MAP_REGIONS) {
433 imx8_mem_map[i].size = 0;
434 imx8_mem_map[i].attrs = 0;
436 puts("Error, need more MEM MAP REGIONS reserved\n");
441 for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
442 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
443 i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
444 imx8_mem_map[i].size, imx8_mem_map[i].attrs);
451 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
452 u64 get_page_table_size(void)
454 u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
458 * For each memory region, the max table size:
459 * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
461 size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
464 * We need to duplicate our page table once to have an emergency pt to
465 * resort to when splitting page tables later on
470 * We may need to split page tables later on if dcache settings change,
471 * so reserve up to 4 (random pick) page tables for that.
479 #if defined(CONFIG_IMX8QM)
480 #define FUSE_MAC0_WORD0 452
481 #define FUSE_MAC0_WORD1 453
482 #define FUSE_MAC1_WORD0 454
483 #define FUSE_MAC1_WORD1 455
484 #elif defined(CONFIG_IMX8QXP)
485 #define FUSE_MAC0_WORD0 708
486 #define FUSE_MAC0_WORD1 709
487 #define FUSE_MAC1_WORD0 710
488 #define FUSE_MAC1_WORD1 711
491 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
493 u32 word[2], val[2] = {};
497 word[0] = FUSE_MAC0_WORD0;
498 word[1] = FUSE_MAC0_WORD1;
500 word[0] = FUSE_MAC1_WORD0;
501 word[1] = FUSE_MAC1_WORD1;
504 for (i = 0; i < 2; i++) {
505 ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
511 mac[1] = val[0] >> 8;
512 mac[2] = val[0] >> 16;
513 mac[3] = val[0] >> 24;
515 mac[5] = val[1] >> 8;
517 debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
518 __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
521 printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
524 u32 get_cpu_rev(void)
529 ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
533 rev = (id >> 5) & 0xf;
534 id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
536 return (id << 12) | rev;