1 // SPDX-License-Identifier: GPL-2.0+
12 #include <dm/device-internal.h>
14 #include <dm/uclass.h>
18 #include <asm/arch/sci/sci.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/arch-imx/cpu.h>
21 #include <asm/armv8/cpu.h>
22 #include <asm/armv8/mmu.h>
23 #include <asm/setup.h>
24 #include <asm/mach-imx/boot_mode.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define BT_PASSOVER_TAG 0x504F
30 struct pass_over_info_t *get_pass_over_info(void)
32 struct pass_over_info_t *p =
33 (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
35 if (p->barker != BT_PASSOVER_TAG ||
36 p->len != sizeof(struct pass_over_info_t))
42 int arch_cpu_init(void)
44 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
45 spl_save_restore_data();
48 #ifdef CONFIG_SPL_BUILD
49 struct pass_over_info_t *pass_over;
51 if (is_soc_rev(CHIP_REV_A)) {
52 pass_over = get_pass_over_info();
53 if (pass_over && pass_over->g_ap_mu == 0) {
55 * When ap_mu is 0, means the U-Boot booted
56 * from first container
58 sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
66 int arch_cpu_init_dm(void)
71 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
73 ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
75 printf("could not get scu %d\n", ret);
80 ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
89 int print_bootinfo(void)
91 enum boot_device bt_dev = get_boot_device();
126 printf("Unknown device %u\n", bt_dev);
133 enum boot_device get_boot_device(void)
135 enum boot_device boot_dev = SD1_BOOT;
139 sc_misc_get_boot_dev(-1, &dev_rsrc);
143 boot_dev = MMC1_BOOT;
152 boot_dev = NAND_BOOT;
155 boot_dev = FLEXSPI_BOOT;
158 boot_dev = SATA_BOOT;
172 #ifdef CONFIG_SERIAL_TAG
173 #define FUSE_UNIQUE_ID_WORD0 16
174 #define FUSE_UNIQUE_ID_WORD1 17
175 void get_board_serial(struct tag_serialnr *serialnr)
178 u32 val1 = 0, val2 = 0;
184 word1 = FUSE_UNIQUE_ID_WORD0;
185 word2 = FUSE_UNIQUE_ID_WORD1;
187 err = sc_misc_otp_fuse_read(-1, word1, &val1);
188 if (err != SC_ERR_NONE) {
189 printf("%s fuse %d read error: %d\n", __func__, word1, err);
193 err = sc_misc_otp_fuse_read(-1, word2, &val2);
194 if (err != SC_ERR_NONE) {
195 printf("%s fuse %d read error: %d\n", __func__, word2, err);
198 serialnr->low = val1;
199 serialnr->high = val2;
201 #endif /*CONFIG_SERIAL_TAG*/
203 #ifdef CONFIG_ENV_IS_IN_MMC
204 __weak int board_mmc_get_env_dev(int devno)
206 return CONFIG_SYS_MMC_ENV_DEV;
209 int mmc_get_env_dev(void)
214 sc_misc_get_boot_dev(-1, &dev_rsrc);
227 /* If not boot from sd/mmc, use default value */
228 return CONFIG_SYS_MMC_ENV_DEV;
231 return board_mmc_get_env_dev(devno);
235 #define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */
237 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
238 sc_faddr_t *addr_end)
240 sc_faddr_t start, end;
244 owned = sc_rm_is_memreg_owned(-1, mr);
246 ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
248 printf("Memreg get info failed, %d\n", ret);
251 debug("0x%llx -- 0x%llx\n", start, end);
261 phys_size_t get_effective_memsize(void)
264 sc_faddr_t start, end, end1, start_aligned;
267 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
269 for (mr = 0; mr < 64; mr++) {
270 err = get_owned_memreg(mr, &start, &end);
272 start_aligned = roundup(start, MEMSTART_ALIGNMENT);
273 /* Too small memory region, not use it */
274 if (start_aligned > end)
277 /* Find the memory region runs the U-Boot */
278 if (start >= PHYS_SDRAM_1 && start <= end1 &&
279 (start <= CONFIG_SYS_TEXT_BASE &&
280 end >= CONFIG_SYS_TEXT_BASE)) {
281 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
283 return (end - PHYS_SDRAM_1 + 1);
285 return PHYS_SDRAM_1_SIZE;
290 return PHYS_SDRAM_1_SIZE;
296 sc_faddr_t start, end, end1, end2;
299 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
300 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
301 for (mr = 0; mr < 64; mr++) {
302 err = get_owned_memreg(mr, &start, &end);
304 start = roundup(start, MEMSTART_ALIGNMENT);
305 /* Too small memory region, not use it */
309 if (start >= PHYS_SDRAM_1 && start <= end1) {
310 if ((end + 1) <= end1)
311 gd->ram_size += end - start + 1;
313 gd->ram_size += end1 - start;
314 } else if (start >= PHYS_SDRAM_2 && start <= end2) {
315 if ((end + 1) <= end2)
316 gd->ram_size += end - start + 1;
318 gd->ram_size += end2 - start;
323 /* If error, set to the default value */
325 gd->ram_size = PHYS_SDRAM_1_SIZE;
326 gd->ram_size += PHYS_SDRAM_2_SIZE;
331 static void dram_bank_sort(int current_bank)
336 while (current_bank > 0) {
337 if (gd->bd->bi_dram[current_bank - 1].start >
338 gd->bd->bi_dram[current_bank].start) {
339 start = gd->bd->bi_dram[current_bank - 1].start;
340 size = gd->bd->bi_dram[current_bank - 1].size;
342 gd->bd->bi_dram[current_bank - 1].start =
343 gd->bd->bi_dram[current_bank].start;
344 gd->bd->bi_dram[current_bank - 1].size =
345 gd->bd->bi_dram[current_bank].size;
347 gd->bd->bi_dram[current_bank].start = start;
348 gd->bd->bi_dram[current_bank].size = size;
354 int dram_init_banksize(void)
357 sc_faddr_t start, end, end1, end2;
361 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
362 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
364 for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
365 err = get_owned_memreg(mr, &start, &end);
367 start = roundup(start, MEMSTART_ALIGNMENT);
368 if (start > end) /* Small memory region, no use it */
371 if (start >= PHYS_SDRAM_1 && start <= end1) {
372 gd->bd->bi_dram[i].start = start;
374 if ((end + 1) <= end1)
375 gd->bd->bi_dram[i].size =
378 gd->bd->bi_dram[i].size = end1 - start;
382 } else if (start >= PHYS_SDRAM_2 && start <= end2) {
383 gd->bd->bi_dram[i].start = start;
385 if ((end + 1) <= end2)
386 gd->bd->bi_dram[i].size =
389 gd->bd->bi_dram[i].size = end2 - start;
397 /* If error, set to the default value */
399 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
400 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
401 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
402 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
408 static u64 get_block_attrs(sc_faddr_t addr_start)
410 u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
411 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
413 if ((addr_start >= PHYS_SDRAM_1 &&
414 addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
415 (addr_start >= PHYS_SDRAM_2 &&
416 addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
417 return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
422 static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
424 sc_faddr_t end1, end2;
426 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
427 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
429 if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
430 if ((addr_end + 1) > end1)
431 return end1 - addr_start;
432 } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
433 if ((addr_end + 1) > end2)
434 return end2 - addr_start;
437 return (addr_end - addr_start + 1);
440 #define MAX_PTE_ENTRIES 512
441 #define MAX_MEM_MAP_REGIONS 16
443 static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
444 struct mm_region *mem_map = imx8_mem_map;
446 void enable_caches(void)
449 sc_faddr_t start, end;
452 /* Create map for registers access from 0x1c000000 to 0x80000000*/
453 imx8_mem_map[0].virt = 0x1c000000UL;
454 imx8_mem_map[0].phys = 0x1c000000UL;
455 imx8_mem_map[0].size = 0x64000000UL;
456 imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
457 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
460 for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
461 err = get_owned_memreg(mr, &start, &end);
463 imx8_mem_map[i].virt = start;
464 imx8_mem_map[i].phys = start;
465 imx8_mem_map[i].size = get_block_size(start, end);
466 imx8_mem_map[i].attrs = get_block_attrs(start);
471 if (i < MAX_MEM_MAP_REGIONS) {
472 imx8_mem_map[i].size = 0;
473 imx8_mem_map[i].attrs = 0;
475 puts("Error, need more MEM MAP REGIONS reserved\n");
480 for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
481 debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
482 i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
483 imx8_mem_map[i].size, imx8_mem_map[i].attrs);
490 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
491 u64 get_page_table_size(void)
493 u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
497 * For each memory region, the max table size:
498 * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
500 size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
503 * We need to duplicate our page table once to have an emergency pt to
504 * resort to when splitting page tables later on
509 * We may need to split page tables later on if dcache settings change,
510 * so reserve up to 4 (random pick) page tables for that.
518 #if defined(CONFIG_IMX8QM)
519 #define FUSE_MAC0_WORD0 452
520 #define FUSE_MAC0_WORD1 453
521 #define FUSE_MAC1_WORD0 454
522 #define FUSE_MAC1_WORD1 455
523 #elif defined(CONFIG_IMX8QXP)
524 #define FUSE_MAC0_WORD0 708
525 #define FUSE_MAC0_WORD1 709
526 #define FUSE_MAC1_WORD0 710
527 #define FUSE_MAC1_WORD1 711
530 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
532 u32 word[2], val[2] = {};
536 word[0] = FUSE_MAC0_WORD0;
537 word[1] = FUSE_MAC0_WORD1;
539 word[0] = FUSE_MAC1_WORD0;
540 word[1] = FUSE_MAC1_WORD1;
543 for (i = 0; i < 2; i++) {
544 ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
550 mac[1] = val[0] >> 8;
551 mac[2] = val[0] >> 16;
552 mac[3] = val[0] >> 24;
554 mac[5] = val[1] >> 8;
556 debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
557 __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
560 printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
563 u32 get_cpu_rev(void)
568 ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
572 rev = (id >> 5) & 0xf;
573 id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
575 return (id << 12) | rev;
578 void board_boot_order(u32 *spl_boot_list)
580 spl_boot_list[0] = spl_boot_device();
582 if (spl_boot_list[0] == BOOT_DEVICE_SPI) {
583 /* Check whether we own the flexspi0, if not, use NOR boot */
584 if (!sc_rm_is_resource_owned(-1, SC_R_FSPI_0))
585 spl_boot_list[0] = BOOT_DEVICE_NOR;