1 // SPDX-License-Identifier: GPL-2.0+
4 * Sascha Hauer, Pengutronix
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
12 #include <linux/errno.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <imx_thermal.h>
20 #include <ipu_pixfmt.h>
24 #ifdef CONFIG_FSL_ESDHC_IMX
25 #include <fsl_esdhc_imx.h>
28 static u32 reset_cause = -1;
30 u32 get_imx_reset_cause(void)
32 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
34 if (reset_cause == -1) {
35 reset_cause = readl(&src_regs->srsr);
36 /* preserve the value for U-Boot proper */
37 #if !defined(CONFIG_SPL_BUILD)
38 writel(reset_cause, &src_regs->srsr);
45 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
46 static char *get_reset_cause(void)
48 switch (get_imx_reset_cause()) {
73 #elif defined(CONFIG_IMX8M)
85 return "unknown reset";
90 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
92 const char *get_imx_type(u32 imxtype)
96 return "8MP"; /* Quad-core version of the imx8mp */
98 return "8MNano";/* Quad-core version of the imx8mn */
100 return "8MMQ"; /* Quad-core version of the imx8mm */
101 case MXC_CPU_IMX8MML:
102 return "8MMQL"; /* Quad-core Lite version of the imx8mm */
103 case MXC_CPU_IMX8MMD:
104 return "8MMD"; /* Dual-core version of the imx8mm */
105 case MXC_CPU_IMX8MMDL:
106 return "8MMDL"; /* Dual-core Lite version of the imx8mm */
107 case MXC_CPU_IMX8MMS:
108 return "8MMS"; /* Single-core version of the imx8mm */
109 case MXC_CPU_IMX8MMSL:
110 return "8MMSL"; /* Single-core Lite version of the imx8mm */
112 return "8MQ"; /* Quad-core version of the imx8m */
114 return "7S"; /* Single-core version of the mx7 */
116 return "7D"; /* Dual-core version of the mx7 */
118 return "6QP"; /* Quad-Plus version of the mx6 */
120 return "6DP"; /* Dual-Plus version of the mx6 */
122 return "6Q"; /* Quad-core version of the mx6 */
124 return "6D"; /* Dual-core version of the mx6 */
126 return "6DL"; /* Dual Lite version of the mx6 */
127 case MXC_CPU_MX6SOLO:
128 return "6SOLO"; /* Solo version of the mx6 */
130 return "6SL"; /* Solo-Lite version of the mx6 */
132 return "6SLL"; /* SLL version of the mx6 */
134 return "6SX"; /* SoloX version of the mx6 */
136 return "6UL"; /* Ultra-Lite version of the mx6 */
138 return "6ULL"; /* ULL version of the mx6 */
140 return "6ULZ"; /* ULZ version of the mx6 */
150 int print_cpuinfo(void)
153 __maybe_unused u32 max_freq;
155 cpurev = get_cpu_rev();
157 #if defined(CONFIG_IMX_THERMAL)
158 struct udevice *thermal_dev;
159 int cpu_tmp, minc, maxc, ret;
161 printf("CPU: Freescale i.MX%s rev%d.%d",
162 get_imx_type((cpurev & 0x1FF000) >> 12),
163 (cpurev & 0x000F0) >> 4,
164 (cpurev & 0x0000F) >> 0);
165 max_freq = get_cpu_speed_grade_hz();
166 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
167 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
169 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
170 mxc_get_clock(MXC_ARM_CLK) / 1000000);
173 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
174 get_imx_type((cpurev & 0x1FF000) >> 12),
175 (cpurev & 0x000F0) >> 4,
176 (cpurev & 0x0000F) >> 0,
177 mxc_get_clock(MXC_ARM_CLK) / 1000000);
180 #if defined(CONFIG_IMX_THERMAL)
182 switch (get_cpu_temp_grade(&minc, &maxc)) {
183 case TEMP_AUTOMOTIVE:
184 puts("Automotive temperature grade ");
186 case TEMP_INDUSTRIAL:
187 puts("Industrial temperature grade ");
189 case TEMP_EXTCOMMERCIAL:
190 puts("Extended Commercial temperature grade ");
193 puts("Commercial temperature grade ");
196 printf("(%dC to %dC)", minc, maxc);
197 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
199 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
202 printf(" at %dC\n", cpu_tmp);
204 debug(" - invalid sensor data\n");
206 debug(" - invalid sensor device\n");
210 printf("Reset cause: %s\n", get_reset_cause());
215 int cpu_eth_init(bd_t *bis)
219 #if defined(CONFIG_FEC_MXC)
220 rc = fecmxc_initialize(bis);
226 #ifdef CONFIG_FSL_ESDHC_IMX
228 * Initializes on-chip MMC controllers.
229 * to override, implement board_mmc_init()
231 int cpu_mmc_init(bd_t *bis)
233 return fsl_esdhc_mmc_init(bis);
237 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
238 u32 get_ahb_clk(void)
240 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
243 reg = __raw_readl(&imx_ccm->cbcdr);
244 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
245 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
247 return get_periph_clk() / (ahb_podf + 1);
251 void arch_preboot_os(void)
253 #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
256 #if defined(CONFIG_SATA)
259 #if defined(CONFIG_MX6)
260 disable_sata_clock();
264 #if defined(CONFIG_VIDEO_IPUV3)
265 /* disable video before launching O/S */
268 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
274 void set_chipselect_size(int const cs_size)
277 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
278 reg = readl(&iomuxc_regs->gpr[1]);
282 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
285 case CS0_64M_CS1_64M:
286 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
289 case CS0_64M_CS1_32M_CS2_32M:
290 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
293 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
294 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
298 printf("Unknown chip select size: %d\n", cs_size);
302 writel(reg, &iomuxc_regs->gpr[1]);
306 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
308 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
309 * defines a 2-bit SPEED_GRADING
311 #define OCOTP_TESTER3_SPEED_SHIFT 8
313 OCOTP_TESTER3_SPEED_GRADE0,
314 OCOTP_TESTER3_SPEED_GRADE1,
315 OCOTP_TESTER3_SPEED_GRADE2,
316 OCOTP_TESTER3_SPEED_GRADE3,
319 u32 get_cpu_speed_grade_hz(void)
321 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
322 struct fuse_bank *bank = &ocotp->bank[1];
323 struct fuse_bank1_regs *fuse =
324 (struct fuse_bank1_regs *)bank->fuse_regs;
327 val = readl(&fuse->tester3);
328 val >>= OCOTP_TESTER3_SPEED_SHIFT;
332 case OCOTP_TESTER3_SPEED_GRADE0:
334 case OCOTP_TESTER3_SPEED_GRADE1:
335 return is_mx7() ? 500000000 : 1000000000;
336 case OCOTP_TESTER3_SPEED_GRADE2:
337 return is_mx7() ? 1000000000 : 1300000000;
338 case OCOTP_TESTER3_SPEED_GRADE3:
339 return is_mx7() ? 1200000000 : 1500000000;
346 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
347 * defines a 2-bit SPEED_GRADING
349 #define OCOTP_TESTER3_TEMP_SHIFT 6
351 u32 get_cpu_temp_grade(int *minc, int *maxc)
353 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
354 struct fuse_bank *bank = &ocotp->bank[1];
355 struct fuse_bank1_regs *fuse =
356 (struct fuse_bank1_regs *)bank->fuse_regs;
359 val = readl(&fuse->tester3);
360 val >>= OCOTP_TESTER3_TEMP_SHIFT;
364 if (val == TEMP_AUTOMOTIVE) {
367 } else if (val == TEMP_INDUSTRIAL) {
370 } else if (val == TEMP_EXTCOMMERCIAL) {
382 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
383 enum boot_device get_boot_device(void)
385 struct bootrom_sw_info **p =
386 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
388 enum boot_device boot_dev = SD1_BOOT;
389 u8 boot_type = (*p)->boot_dev_type;
390 u8 boot_instance = (*p)->boot_dev_instance;
394 boot_dev = boot_instance + SD1_BOOT;
397 boot_dev = boot_instance + MMC1_BOOT;
400 boot_dev = NAND_BOOT;
403 boot_dev = QSPI_BOOT;
406 boot_dev = WEIM_NOR_BOOT;
408 case BOOT_TYPE_SPINOR:
409 boot_dev = SPI_NOR_BOOT;
424 #ifdef CONFIG_NXP_BOARD_REVISION
425 int nxp_board_rev(void)
428 * Get Board ID information from OCOTP_GP1[15:8]
433 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
434 struct fuse_bank *bank = &ocotp->bank[4];
435 struct fuse_bank4_regs *fuse =
436 (struct fuse_bank4_regs *)bank->fuse_regs;
438 return (readl(&fuse->gp1) >> 8 & 0x0F);
441 char nxp_board_rev_string(void)
443 const char *rev = "A";
445 return (*rev + nxp_board_rev() - 1);