1 // SPDX-License-Identifier: GPL-2.0+
4 * Sascha Hauer, Pengutronix
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
15 #include <linux/errno.h>
17 #include <asm/arch/imx-regs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/arch/crm_regs.h>
21 #include <asm/mach-imx/boot_mode.h>
22 #include <imx_thermal.h>
23 #include <ipu_pixfmt.h>
27 #ifdef CONFIG_FSL_ESDHC_IMX
28 #include <fsl_esdhc_imx.h>
31 static u32 reset_cause = -1;
33 u32 get_imx_reset_cause(void)
35 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
37 if (reset_cause == -1) {
38 reset_cause = readl(&src_regs->srsr);
39 /* preserve the value for U-Boot proper */
40 #if !defined(CONFIG_SPL_BUILD)
41 writel(reset_cause, &src_regs->srsr);
48 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
49 static char *get_reset_cause(void)
51 switch (get_imx_reset_cause()) {
76 #elif defined(CONFIG_IMX8M)
88 return "unknown reset";
93 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
95 const char *get_imx_type(u32 imxtype)
99 return "8MP"; /* Quad-core version of the imx8mp */
101 return "8MNano Quad"; /* Quad-core version */
102 case MXC_CPU_IMX8MND:
103 return "8MNano Dual"; /* Dual-core version */
104 case MXC_CPU_IMX8MNS:
105 return "8MNano Solo"; /* Single-core version */
106 case MXC_CPU_IMX8MNL:
107 return "8MNano QuadLite"; /* Quad-core Lite version */
108 case MXC_CPU_IMX8MNDL:
109 return "8MNano DualLite"; /* Dual-core Lite version */
110 case MXC_CPU_IMX8MNSL:
111 return "8MNano SoloLite"; /* Single-core Lite version */
113 return "8MMQ"; /* Quad-core version of the imx8mm */
114 case MXC_CPU_IMX8MML:
115 return "8MMQL"; /* Quad-core Lite version of the imx8mm */
116 case MXC_CPU_IMX8MMD:
117 return "8MMD"; /* Dual-core version of the imx8mm */
118 case MXC_CPU_IMX8MMDL:
119 return "8MMDL"; /* Dual-core Lite version of the imx8mm */
120 case MXC_CPU_IMX8MMS:
121 return "8MMS"; /* Single-core version of the imx8mm */
122 case MXC_CPU_IMX8MMSL:
123 return "8MMSL"; /* Single-core Lite version of the imx8mm */
125 return "8MQ"; /* Quad-core version of the imx8mq */
126 case MXC_CPU_IMX8MQL:
127 return "8MQLite"; /* Quad-core Lite version of the imx8mq */
129 return "8MD"; /* Dual-core version of the imx8mq */
131 return "7S"; /* Single-core version of the mx7 */
133 return "7D"; /* Dual-core version of the mx7 */
135 return "6QP"; /* Quad-Plus version of the mx6 */
137 return "6DP"; /* Dual-Plus version of the mx6 */
139 return "6Q"; /* Quad-core version of the mx6 */
141 return "6D"; /* Dual-core version of the mx6 */
143 return "6DL"; /* Dual Lite version of the mx6 */
144 case MXC_CPU_MX6SOLO:
145 return "6SOLO"; /* Solo version of the mx6 */
147 return "6SL"; /* Solo-Lite version of the mx6 */
149 return "6SLL"; /* SLL version of the mx6 */
151 return "6SX"; /* SoloX version of the mx6 */
153 return "6UL"; /* Ultra-Lite version of the mx6 */
155 return "6ULL"; /* ULL version of the mx6 */
157 return "6ULZ"; /* ULZ version of the mx6 */
167 int print_cpuinfo(void)
170 __maybe_unused u32 max_freq;
172 cpurev = get_cpu_rev();
174 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
175 struct udevice *thermal_dev;
176 int cpu_tmp, minc, maxc, ret;
178 printf("CPU: Freescale i.MX%s rev%d.%d",
179 get_imx_type((cpurev & 0x1FF000) >> 12),
180 (cpurev & 0x000F0) >> 4,
181 (cpurev & 0x0000F) >> 0);
182 max_freq = get_cpu_speed_grade_hz();
183 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
184 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
186 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
187 mxc_get_clock(MXC_ARM_CLK) / 1000000);
190 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
191 get_imx_type((cpurev & 0x1FF000) >> 12),
192 (cpurev & 0x000F0) >> 4,
193 (cpurev & 0x0000F) >> 0,
194 mxc_get_clock(MXC_ARM_CLK) / 1000000);
197 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
199 switch (get_cpu_temp_grade(&minc, &maxc)) {
200 case TEMP_AUTOMOTIVE:
201 puts("Automotive temperature grade ");
203 case TEMP_INDUSTRIAL:
204 puts("Industrial temperature grade ");
206 case TEMP_EXTCOMMERCIAL:
207 puts("Extended Commercial temperature grade ");
210 puts("Commercial temperature grade ");
213 printf("(%dC to %dC)", minc, maxc);
214 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
216 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
219 printf(" at %dC\n", cpu_tmp);
221 debug(" - invalid sensor data\n");
223 debug(" - invalid sensor device\n");
227 printf("Reset cause: %s\n", get_reset_cause());
232 int cpu_eth_init(bd_t *bis)
236 #if defined(CONFIG_FEC_MXC)
237 rc = fecmxc_initialize(bis);
243 #ifdef CONFIG_FSL_ESDHC_IMX
245 * Initializes on-chip MMC controllers.
246 * to override, implement board_mmc_init()
248 int cpu_mmc_init(bd_t *bis)
250 return fsl_esdhc_mmc_init(bis);
254 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
255 u32 get_ahb_clk(void)
257 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
260 reg = __raw_readl(&imx_ccm->cbcdr);
261 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
262 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
264 return get_periph_clk() / (ahb_podf + 1);
268 void arch_preboot_os(void)
270 #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
273 #if defined(CONFIG_SATA)
276 #if defined(CONFIG_MX6)
277 disable_sata_clock();
281 #if defined(CONFIG_VIDEO_IPUV3)
282 /* disable video before launching O/S */
285 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
291 void set_chipselect_size(int const cs_size)
294 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
295 reg = readl(&iomuxc_regs->gpr[1]);
299 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
302 case CS0_64M_CS1_64M:
303 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
306 case CS0_64M_CS1_32M_CS2_32M:
307 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
310 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
311 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
315 printf("Unknown chip select size: %d\n", cs_size);
319 writel(reg, &iomuxc_regs->gpr[1]);
323 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
325 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
326 * defines a 2-bit SPEED_GRADING
328 #define OCOTP_TESTER3_SPEED_SHIFT 8
330 OCOTP_TESTER3_SPEED_GRADE0,
331 OCOTP_TESTER3_SPEED_GRADE1,
332 OCOTP_TESTER3_SPEED_GRADE2,
333 OCOTP_TESTER3_SPEED_GRADE3,
334 OCOTP_TESTER3_SPEED_GRADE4,
337 u32 get_cpu_speed_grade_hz(void)
339 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
340 struct fuse_bank *bank = &ocotp->bank[1];
341 struct fuse_bank1_regs *fuse =
342 (struct fuse_bank1_regs *)bank->fuse_regs;
345 val = readl(&fuse->tester3);
346 val >>= OCOTP_TESTER3_SPEED_SHIFT;
348 if (is_imx8mn() || is_imx8mp()) {
350 return 2300000000 - val * 100000000;
359 case OCOTP_TESTER3_SPEED_GRADE0:
361 case OCOTP_TESTER3_SPEED_GRADE1:
362 return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
363 case OCOTP_TESTER3_SPEED_GRADE2:
364 return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
365 case OCOTP_TESTER3_SPEED_GRADE3:
366 return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
367 case OCOTP_TESTER3_SPEED_GRADE4:
375 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
376 * defines a 2-bit SPEED_GRADING
378 #define OCOTP_TESTER3_TEMP_SHIFT 6
380 u32 get_cpu_temp_grade(int *minc, int *maxc)
382 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
383 struct fuse_bank *bank = &ocotp->bank[1];
384 struct fuse_bank1_regs *fuse =
385 (struct fuse_bank1_regs *)bank->fuse_regs;
388 val = readl(&fuse->tester3);
389 val >>= OCOTP_TESTER3_TEMP_SHIFT;
393 if (val == TEMP_AUTOMOTIVE) {
396 } else if (val == TEMP_INDUSTRIAL) {
399 } else if (val == TEMP_EXTCOMMERCIAL) {
411 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
412 enum boot_device get_boot_device(void)
414 struct bootrom_sw_info **p =
415 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
417 enum boot_device boot_dev = SD1_BOOT;
418 u8 boot_type = (*p)->boot_dev_type;
419 u8 boot_instance = (*p)->boot_dev_instance;
423 boot_dev = boot_instance + SD1_BOOT;
426 boot_dev = boot_instance + MMC1_BOOT;
429 boot_dev = NAND_BOOT;
432 boot_dev = QSPI_BOOT;
435 boot_dev = WEIM_NOR_BOOT;
437 case BOOT_TYPE_SPINOR:
438 boot_dev = SPI_NOR_BOOT;
453 #ifdef CONFIG_NXP_BOARD_REVISION
454 int nxp_board_rev(void)
457 * Get Board ID information from OCOTP_GP1[15:8]
462 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
463 struct fuse_bank *bank = &ocotp->bank[4];
464 struct fuse_bank4_regs *fuse =
465 (struct fuse_bank4_regs *)bank->fuse_regs;
467 return (readl(&fuse->gp1) >> 8 & 0x0F);
470 char nxp_board_rev_string(void)
472 const char *rev = "A";
474 return (*rev + nxp_board_rev() - 1);