1 // SPDX-License-Identifier: GPL-2.0+
4 * Sascha Hauer, Pengutronix
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
12 #include <linux/errno.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <imx_thermal.h>
20 #include <ipu_pixfmt.h>
24 #ifdef CONFIG_FSL_ESDHC_IMX
25 #include <fsl_esdhc_imx.h>
28 static u32 reset_cause = -1;
30 u32 get_imx_reset_cause(void)
32 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
34 if (reset_cause == -1) {
35 reset_cause = readl(&src_regs->srsr);
36 /* preserve the value for U-Boot proper */
37 #if !defined(CONFIG_SPL_BUILD)
38 writel(reset_cause, &src_regs->srsr);
45 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
46 static char *get_reset_cause(void)
48 switch (get_imx_reset_cause()) {
73 #elif defined(CONFIG_IMX8M)
85 return "unknown reset";
90 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
91 #if defined(CONFIG_MX53)
92 #define MEMCTL_BASE ESDCTL_BASE_ADDR
94 #define MEMCTL_BASE MMDC_P0_BASE_ADDR
96 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
97 static const unsigned char bank_lookup[] = {3, 2};
99 /* these MMDC registers are common to the IMX53 and IMX6 */
100 struct esd_mmdc_regs {
110 #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
111 #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
112 #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
113 #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
114 #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
117 * imx_ddr_size - return size in bytes of DRAM according MMDC config
118 * The MMDC MDCTL register holds the number of bits for row, col, and data
119 * width and the MMDC MDMISC register holds the number of banks. Combine
120 * all these bits to determine the meme size the MMDC has been configured for
122 unsigned imx_ddr_size(void)
124 struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
125 unsigned ctl = readl(&mem->ctl);
126 unsigned misc = readl(&mem->misc);
127 int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
129 bits += ESD_MMDC_CTL_GET_ROW(ctl);
130 bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
131 bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
132 bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
133 bits += ESD_MMDC_CTL_GET_CS1(ctl);
135 /* The MX6 can do only 3840 MiB of DRAM */
143 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
145 const char *get_imx_type(u32 imxtype)
149 return "8MMQ"; /* Quad-core version of the imx8mm */
150 case MXC_CPU_IMX8MML:
151 return "8MMQL"; /* Quad-core Lite version of the imx8mm */
152 case MXC_CPU_IMX8MMD:
153 return "8MMD"; /* Dual-core version of the imx8mm */
154 case MXC_CPU_IMX8MMDL:
155 return "8MMDL"; /* Dual-core Lite version of the imx8mm */
156 case MXC_CPU_IMX8MMS:
157 return "8MMS"; /* Single-core version of the imx8mm */
158 case MXC_CPU_IMX8MMSL:
159 return "8MMSL"; /* Single-core Lite version of the imx8mm */
161 return "8MQ"; /* Quad-core version of the imx8m */
163 return "7S"; /* Single-core version of the mx7 */
165 return "7D"; /* Dual-core version of the mx7 */
167 return "6QP"; /* Quad-Plus version of the mx6 */
169 return "6DP"; /* Dual-Plus version of the mx6 */
171 return "6Q"; /* Quad-core version of the mx6 */
173 return "6D"; /* Dual-core version of the mx6 */
175 return "6DL"; /* Dual Lite version of the mx6 */
176 case MXC_CPU_MX6SOLO:
177 return "6SOLO"; /* Solo version of the mx6 */
179 return "6SL"; /* Solo-Lite version of the mx6 */
181 return "6SLL"; /* SLL version of the mx6 */
183 return "6SX"; /* SoloX version of the mx6 */
185 return "6UL"; /* Ultra-Lite version of the mx6 */
187 return "6ULL"; /* ULL version of the mx6 */
189 return "6ULZ"; /* ULZ version of the mx6 */
199 int print_cpuinfo(void)
202 __maybe_unused u32 max_freq;
204 cpurev = get_cpu_rev();
206 #if defined(CONFIG_IMX_THERMAL)
207 struct udevice *thermal_dev;
208 int cpu_tmp, minc, maxc, ret;
210 printf("CPU: Freescale i.MX%s rev%d.%d",
211 get_imx_type((cpurev & 0xFF000) >> 12),
212 (cpurev & 0x000F0) >> 4,
213 (cpurev & 0x0000F) >> 0);
214 max_freq = get_cpu_speed_grade_hz();
215 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
216 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
218 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
219 mxc_get_clock(MXC_ARM_CLK) / 1000000);
222 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
223 get_imx_type((cpurev & 0xFF000) >> 12),
224 (cpurev & 0x000F0) >> 4,
225 (cpurev & 0x0000F) >> 0,
226 mxc_get_clock(MXC_ARM_CLK) / 1000000);
229 #if defined(CONFIG_IMX_THERMAL)
231 switch (get_cpu_temp_grade(&minc, &maxc)) {
232 case TEMP_AUTOMOTIVE:
233 puts("Automotive temperature grade ");
235 case TEMP_INDUSTRIAL:
236 puts("Industrial temperature grade ");
238 case TEMP_EXTCOMMERCIAL:
239 puts("Extended Commercial temperature grade ");
242 puts("Commercial temperature grade ");
245 printf("(%dC to %dC)", minc, maxc);
246 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
248 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
251 printf(" at %dC\n", cpu_tmp);
253 debug(" - invalid sensor data\n");
255 debug(" - invalid sensor device\n");
259 printf("Reset cause: %s\n", get_reset_cause());
264 int cpu_eth_init(bd_t *bis)
268 #if defined(CONFIG_FEC_MXC)
269 rc = fecmxc_initialize(bis);
275 #ifdef CONFIG_FSL_ESDHC_IMX
277 * Initializes on-chip MMC controllers.
278 * to override, implement board_mmc_init()
280 int cpu_mmc_init(bd_t *bis)
282 return fsl_esdhc_mmc_init(bis);
286 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
287 u32 get_ahb_clk(void)
289 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
292 reg = __raw_readl(&imx_ccm->cbcdr);
293 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
294 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
296 return get_periph_clk() / (ahb_podf + 1);
300 void arch_preboot_os(void)
302 #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
305 #if defined(CONFIG_SATA)
308 #if defined(CONFIG_MX6)
309 disable_sata_clock();
313 #if defined(CONFIG_VIDEO_IPUV3)
314 /* disable video before launching O/S */
317 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
323 void set_chipselect_size(int const cs_size)
326 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
327 reg = readl(&iomuxc_regs->gpr[1]);
331 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
334 case CS0_64M_CS1_64M:
335 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
338 case CS0_64M_CS1_32M_CS2_32M:
339 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
342 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
343 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
347 printf("Unknown chip select size: %d\n", cs_size);
351 writel(reg, &iomuxc_regs->gpr[1]);
355 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
357 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
358 * defines a 2-bit SPEED_GRADING
360 #define OCOTP_TESTER3_SPEED_SHIFT 8
362 OCOTP_TESTER3_SPEED_GRADE0,
363 OCOTP_TESTER3_SPEED_GRADE1,
364 OCOTP_TESTER3_SPEED_GRADE2,
365 OCOTP_TESTER3_SPEED_GRADE3,
368 u32 get_cpu_speed_grade_hz(void)
370 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
371 struct fuse_bank *bank = &ocotp->bank[1];
372 struct fuse_bank1_regs *fuse =
373 (struct fuse_bank1_regs *)bank->fuse_regs;
376 val = readl(&fuse->tester3);
377 val >>= OCOTP_TESTER3_SPEED_SHIFT;
381 case OCOTP_TESTER3_SPEED_GRADE0:
383 case OCOTP_TESTER3_SPEED_GRADE1:
384 return is_mx7() ? 500000000 : 1000000000;
385 case OCOTP_TESTER3_SPEED_GRADE2:
386 return is_mx7() ? 1000000000 : 1300000000;
387 case OCOTP_TESTER3_SPEED_GRADE3:
388 return is_mx7() ? 1200000000 : 1500000000;
395 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
396 * defines a 2-bit SPEED_GRADING
398 #define OCOTP_TESTER3_TEMP_SHIFT 6
400 u32 get_cpu_temp_grade(int *minc, int *maxc)
402 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
403 struct fuse_bank *bank = &ocotp->bank[1];
404 struct fuse_bank1_regs *fuse =
405 (struct fuse_bank1_regs *)bank->fuse_regs;
408 val = readl(&fuse->tester3);
409 val >>= OCOTP_TESTER3_TEMP_SHIFT;
413 if (val == TEMP_AUTOMOTIVE) {
416 } else if (val == TEMP_INDUSTRIAL) {
419 } else if (val == TEMP_EXTCOMMERCIAL) {
431 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
432 enum boot_device get_boot_device(void)
434 struct bootrom_sw_info **p =
435 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
437 enum boot_device boot_dev = SD1_BOOT;
438 u8 boot_type = (*p)->boot_dev_type;
439 u8 boot_instance = (*p)->boot_dev_instance;
443 boot_dev = boot_instance + SD1_BOOT;
446 boot_dev = boot_instance + MMC1_BOOT;
449 boot_dev = NAND_BOOT;
452 boot_dev = QSPI_BOOT;
455 boot_dev = WEIM_NOR_BOOT;
457 case BOOT_TYPE_SPINOR:
458 boot_dev = SPI_NOR_BOOT;
473 #ifdef CONFIG_NXP_BOARD_REVISION
474 int nxp_board_rev(void)
477 * Get Board ID information from OCOTP_GP1[15:8]
482 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
483 struct fuse_bank *bank = &ocotp->bank[4];
484 struct fuse_bank4_regs *fuse =
485 (struct fuse_bank4_regs *)bank->fuse_regs;
487 return (readl(&fuse->gp1) >> 8 & 0x0F);
490 char nxp_board_rev_string(void)
492 const char *rev = "A";
494 return (*rev + nxp_board_rev() - 1);