1 // SPDX-License-Identifier: GPL-2.0+
4 * Sascha Hauer, Pengutronix
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
12 #include <linux/errno.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <imx_thermal.h>
20 #include <ipu_pixfmt.h>
24 #ifdef CONFIG_FSL_ESDHC
25 #include <fsl_esdhc.h>
28 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
29 static u32 reset_cause = -1;
31 static char *get_reset_cause(void)
34 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
36 cause = readl(&src_regs->srsr);
37 writel(cause, &src_regs->srsr);
65 #elif defined(CONFIG_IMX8M)
77 return "unknown reset";
81 u32 get_imx_reset_cause(void)
87 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
88 #if defined(CONFIG_MX53)
89 #define MEMCTL_BASE ESDCTL_BASE_ADDR
91 #define MEMCTL_BASE MMDC_P0_BASE_ADDR
93 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
94 static const unsigned char bank_lookup[] = {3, 2};
96 /* these MMDC registers are common to the IMX53 and IMX6 */
97 struct esd_mmdc_regs {
107 #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
108 #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
109 #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
110 #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
111 #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
114 * imx_ddr_size - return size in bytes of DRAM according MMDC config
115 * The MMDC MDCTL register holds the number of bits for row, col, and data
116 * width and the MMDC MDMISC register holds the number of banks. Combine
117 * all these bits to determine the meme size the MMDC has been configured for
119 unsigned imx_ddr_size(void)
121 struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
122 unsigned ctl = readl(&mem->ctl);
123 unsigned misc = readl(&mem->misc);
124 int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
126 bits += ESD_MMDC_CTL_GET_ROW(ctl);
127 bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
128 bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
129 bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
130 bits += ESD_MMDC_CTL_GET_CS1(ctl);
132 /* The MX6 can do only 3840 MiB of DRAM */
140 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
142 const char *get_imx_type(u32 imxtype)
146 return "8MQ"; /* Quad-core version of the imx8m */
148 return "7S"; /* Single-core version of the mx7 */
150 return "7D"; /* Dual-core version of the mx7 */
152 return "6QP"; /* Quad-Plus version of the mx6 */
154 return "6DP"; /* Dual-Plus version of the mx6 */
156 return "6Q"; /* Quad-core version of the mx6 */
158 return "6D"; /* Dual-core version of the mx6 */
160 return "6DL"; /* Dual Lite version of the mx6 */
161 case MXC_CPU_MX6SOLO:
162 return "6SOLO"; /* Solo version of the mx6 */
164 return "6SL"; /* Solo-Lite version of the mx6 */
166 return "6SLL"; /* SLL version of the mx6 */
168 return "6SX"; /* SoloX version of the mx6 */
170 return "6UL"; /* Ultra-Lite version of the mx6 */
172 return "6ULL"; /* ULL version of the mx6 */
182 int print_cpuinfo(void)
185 __maybe_unused u32 max_freq;
187 cpurev = get_cpu_rev();
189 #if defined(CONFIG_IMX_THERMAL)
190 struct udevice *thermal_dev;
191 int cpu_tmp, minc, maxc, ret;
193 printf("CPU: Freescale i.MX%s rev%d.%d",
194 get_imx_type((cpurev & 0xFF000) >> 12),
195 (cpurev & 0x000F0) >> 4,
196 (cpurev & 0x0000F) >> 0);
197 max_freq = get_cpu_speed_grade_hz();
198 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
199 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
201 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
202 mxc_get_clock(MXC_ARM_CLK) / 1000000);
205 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
206 get_imx_type((cpurev & 0xFF000) >> 12),
207 (cpurev & 0x000F0) >> 4,
208 (cpurev & 0x0000F) >> 0,
209 mxc_get_clock(MXC_ARM_CLK) / 1000000);
212 #if defined(CONFIG_IMX_THERMAL)
214 switch (get_cpu_temp_grade(&minc, &maxc)) {
215 case TEMP_AUTOMOTIVE:
216 puts("Automotive temperature grade ");
218 case TEMP_INDUSTRIAL:
219 puts("Industrial temperature grade ");
221 case TEMP_EXTCOMMERCIAL:
222 puts("Extended Commercial temperature grade ");
225 puts("Commercial temperature grade ");
228 printf("(%dC to %dC)", minc, maxc);
229 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
231 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
234 printf(" at %dC\n", cpu_tmp);
236 debug(" - invalid sensor data\n");
238 debug(" - invalid sensor device\n");
242 printf("Reset cause: %s\n", get_reset_cause());
247 int cpu_eth_init(bd_t *bis)
251 #if defined(CONFIG_FEC_MXC)
252 rc = fecmxc_initialize(bis);
258 #ifdef CONFIG_FSL_ESDHC
260 * Initializes on-chip MMC controllers.
261 * to override, implement board_mmc_init()
263 int cpu_mmc_init(bd_t *bis)
265 return fsl_esdhc_mmc_init(bis);
269 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
270 u32 get_ahb_clk(void)
272 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
275 reg = __raw_readl(&imx_ccm->cbcdr);
276 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
277 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
279 return get_periph_clk() / (ahb_podf + 1);
283 void arch_preboot_os(void)
285 #if defined(CONFIG_PCIE_IMX)
288 #if defined(CONFIG_SATA)
290 #if defined(CONFIG_MX6)
291 disable_sata_clock();
294 #if defined(CONFIG_VIDEO_IPUV3)
295 /* disable video before launching O/S */
298 #if defined(CONFIG_VIDEO_MXS)
304 void set_chipselect_size(int const cs_size)
307 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
308 reg = readl(&iomuxc_regs->gpr[1]);
312 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
315 case CS0_64M_CS1_64M:
316 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
319 case CS0_64M_CS1_32M_CS2_32M:
320 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
323 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
324 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
328 printf("Unknown chip select size: %d\n", cs_size);
332 writel(reg, &iomuxc_regs->gpr[1]);
336 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
338 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
339 * defines a 2-bit SPEED_GRADING
341 #define OCOTP_TESTER3_SPEED_SHIFT 8
343 OCOTP_TESTER3_SPEED_GRADE0,
344 OCOTP_TESTER3_SPEED_GRADE1,
345 OCOTP_TESTER3_SPEED_GRADE2,
346 OCOTP_TESTER3_SPEED_GRADE3,
349 u32 get_cpu_speed_grade_hz(void)
351 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
352 struct fuse_bank *bank = &ocotp->bank[1];
353 struct fuse_bank1_regs *fuse =
354 (struct fuse_bank1_regs *)bank->fuse_regs;
357 val = readl(&fuse->tester3);
358 val >>= OCOTP_TESTER3_SPEED_SHIFT;
362 case OCOTP_TESTER3_SPEED_GRADE0:
364 case OCOTP_TESTER3_SPEED_GRADE1:
365 return is_mx7() ? 500000000 : 1000000000;
366 case OCOTP_TESTER3_SPEED_GRADE2:
367 return is_mx7() ? 1000000000 : 1300000000;
368 case OCOTP_TESTER3_SPEED_GRADE3:
369 return is_mx7() ? 1200000000 : 1500000000;
376 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
377 * defines a 2-bit SPEED_GRADING
379 #define OCOTP_TESTER3_TEMP_SHIFT 6
381 u32 get_cpu_temp_grade(int *minc, int *maxc)
383 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
384 struct fuse_bank *bank = &ocotp->bank[1];
385 struct fuse_bank1_regs *fuse =
386 (struct fuse_bank1_regs *)bank->fuse_regs;
389 val = readl(&fuse->tester3);
390 val >>= OCOTP_TESTER3_TEMP_SHIFT;
394 if (val == TEMP_AUTOMOTIVE) {
397 } else if (val == TEMP_INDUSTRIAL) {
400 } else if (val == TEMP_EXTCOMMERCIAL) {
412 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
413 enum boot_device get_boot_device(void)
415 struct bootrom_sw_info **p =
416 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
418 enum boot_device boot_dev = SD1_BOOT;
419 u8 boot_type = (*p)->boot_dev_type;
420 u8 boot_instance = (*p)->boot_dev_instance;
424 boot_dev = boot_instance + SD1_BOOT;
427 boot_dev = boot_instance + MMC1_BOOT;
430 boot_dev = NAND_BOOT;
433 boot_dev = QSPI_BOOT;
436 boot_dev = WEIM_NOR_BOOT;
438 case BOOT_TYPE_SPINOR:
439 boot_dev = SPI_NOR_BOOT;
454 #ifdef CONFIG_NXP_BOARD_REVISION
455 int nxp_board_rev(void)
458 * Get Board ID information from OCOTP_GP1[15:8]
463 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
464 struct fuse_bank *bank = &ocotp->bank[4];
465 struct fuse_bank4_regs *fuse =
466 (struct fuse_bank4_regs *)bank->fuse_regs;
468 return (readl(&fuse->gp1) >> 8 & 0x0F);
471 char nxp_board_rev_string(void)
473 const char *rev = "A";
475 return (*rev + nxp_board_rev() - 1);