3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/errno.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/crm_regs.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <imx_thermal.h>
21 #include <ipu_pixfmt.h>
25 #ifdef CONFIG_FSL_ESDHC
26 #include <fsl_esdhc.h>
29 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
30 static u32 reset_cause = -1;
32 static char *get_reset_cause(void)
35 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
37 cause = readl(&src_regs->srsr);
38 writel(cause, &src_regs->srsr);
66 #elif defined(CONFIG_MX8M)
78 return "unknown reset";
82 u32 get_imx_reset_cause(void)
88 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
89 #if defined(CONFIG_MX53)
90 #define MEMCTL_BASE ESDCTL_BASE_ADDR
92 #define MEMCTL_BASE MMDC_P0_BASE_ADDR
94 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
95 static const unsigned char bank_lookup[] = {3, 2};
97 /* these MMDC registers are common to the IMX53 and IMX6 */
98 struct esd_mmdc_regs {
108 #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
109 #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
110 #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
111 #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
112 #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
115 * imx_ddr_size - return size in bytes of DRAM according MMDC config
116 * The MMDC MDCTL register holds the number of bits for row, col, and data
117 * width and the MMDC MDMISC register holds the number of banks. Combine
118 * all these bits to determine the meme size the MMDC has been configured for
120 unsigned imx_ddr_size(void)
122 struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
123 unsigned ctl = readl(&mem->ctl);
124 unsigned misc = readl(&mem->misc);
125 int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
127 bits += ESD_MMDC_CTL_GET_ROW(ctl);
128 bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
129 bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
130 bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
131 bits += ESD_MMDC_CTL_GET_CS1(ctl);
133 /* The MX6 can do only 3840 MiB of DRAM */
141 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
143 const char *get_imx_type(u32 imxtype)
147 return "8MQ"; /* Quad-core version of the mx8m */
149 return "7S"; /* Single-core version of the mx7 */
151 return "7D"; /* Dual-core version of the mx7 */
153 return "6QP"; /* Quad-Plus version of the mx6 */
155 return "6DP"; /* Dual-Plus version of the mx6 */
157 return "6Q"; /* Quad-core version of the mx6 */
159 return "6D"; /* Dual-core version of the mx6 */
161 return "6DL"; /* Dual Lite version of the mx6 */
162 case MXC_CPU_MX6SOLO:
163 return "6SOLO"; /* Solo version of the mx6 */
165 return "6SL"; /* Solo-Lite version of the mx6 */
167 return "6SLL"; /* SLL version of the mx6 */
169 return "6SX"; /* SoloX version of the mx6 */
171 return "6UL"; /* Ultra-Lite version of the mx6 */
173 return "6ULL"; /* ULL version of the mx6 */
183 int print_cpuinfo(void)
186 __maybe_unused u32 max_freq;
188 cpurev = get_cpu_rev();
190 #if defined(CONFIG_IMX_THERMAL)
191 struct udevice *thermal_dev;
192 int cpu_tmp, minc, maxc, ret;
194 printf("CPU: Freescale i.MX%s rev%d.%d",
195 get_imx_type((cpurev & 0xFF000) >> 12),
196 (cpurev & 0x000F0) >> 4,
197 (cpurev & 0x0000F) >> 0);
198 max_freq = get_cpu_speed_grade_hz();
199 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
200 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
202 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
203 mxc_get_clock(MXC_ARM_CLK) / 1000000);
206 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
207 get_imx_type((cpurev & 0xFF000) >> 12),
208 (cpurev & 0x000F0) >> 4,
209 (cpurev & 0x0000F) >> 0,
210 mxc_get_clock(MXC_ARM_CLK) / 1000000);
213 #if defined(CONFIG_IMX_THERMAL)
215 switch (get_cpu_temp_grade(&minc, &maxc)) {
216 case TEMP_AUTOMOTIVE:
217 puts("Automotive temperature grade ");
219 case TEMP_INDUSTRIAL:
220 puts("Industrial temperature grade ");
222 case TEMP_EXTCOMMERCIAL:
223 puts("Extended Commercial temperature grade ");
226 puts("Commercial temperature grade ");
229 printf("(%dC to %dC)", minc, maxc);
230 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
232 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
235 printf(" at %dC\n", cpu_tmp);
237 debug(" - invalid sensor data\n");
239 debug(" - invalid sensor device\n");
243 printf("Reset cause: %s\n", get_reset_cause());
248 int cpu_eth_init(bd_t *bis)
252 #if defined(CONFIG_FEC_MXC)
253 rc = fecmxc_initialize(bis);
259 #ifdef CONFIG_FSL_ESDHC
261 * Initializes on-chip MMC controllers.
262 * to override, implement board_mmc_init()
264 int cpu_mmc_init(bd_t *bis)
266 return fsl_esdhc_mmc_init(bis);
270 #if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M))
271 u32 get_ahb_clk(void)
273 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
276 reg = __raw_readl(&imx_ccm->cbcdr);
277 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
278 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
280 return get_periph_clk() / (ahb_podf + 1);
284 void arch_preboot_os(void)
286 #if defined(CONFIG_PCIE_IMX)
289 #if defined(CONFIG_SATA)
291 #if defined(CONFIG_MX6)
292 disable_sata_clock();
295 #if defined(CONFIG_VIDEO_IPUV3)
296 /* disable video before launching O/S */
299 #if defined(CONFIG_VIDEO_MXS)
305 void set_chipselect_size(int const cs_size)
308 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
309 reg = readl(&iomuxc_regs->gpr[1]);
313 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
316 case CS0_64M_CS1_64M:
317 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
320 case CS0_64M_CS1_32M_CS2_32M:
321 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
324 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
325 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
329 printf("Unknown chip select size: %d\n", cs_size);
333 writel(reg, &iomuxc_regs->gpr[1]);
337 #if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
339 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
340 * defines a 2-bit SPEED_GRADING
342 #define OCOTP_TESTER3_SPEED_SHIFT 8
344 OCOTP_TESTER3_SPEED_GRADE0,
345 OCOTP_TESTER3_SPEED_GRADE1,
346 OCOTP_TESTER3_SPEED_GRADE2,
347 OCOTP_TESTER3_SPEED_GRADE3,
350 u32 get_cpu_speed_grade_hz(void)
352 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
353 struct fuse_bank *bank = &ocotp->bank[1];
354 struct fuse_bank1_regs *fuse =
355 (struct fuse_bank1_regs *)bank->fuse_regs;
358 val = readl(&fuse->tester3);
359 val >>= OCOTP_TESTER3_SPEED_SHIFT;
363 case OCOTP_TESTER3_SPEED_GRADE0:
365 case OCOTP_TESTER3_SPEED_GRADE1:
366 return is_mx7() ? 500000000 : 1000000000;
367 case OCOTP_TESTER3_SPEED_GRADE2:
368 return is_mx7() ? 1000000000 : 1300000000;
369 case OCOTP_TESTER3_SPEED_GRADE3:
370 return is_mx7() ? 1200000000 : 1500000000;
377 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
378 * defines a 2-bit SPEED_GRADING
380 #define OCOTP_TESTER3_TEMP_SHIFT 6
382 u32 get_cpu_temp_grade(int *minc, int *maxc)
384 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
385 struct fuse_bank *bank = &ocotp->bank[1];
386 struct fuse_bank1_regs *fuse =
387 (struct fuse_bank1_regs *)bank->fuse_regs;
390 val = readl(&fuse->tester3);
391 val >>= OCOTP_TESTER3_TEMP_SHIFT;
395 if (val == TEMP_AUTOMOTIVE) {
398 } else if (val == TEMP_INDUSTRIAL) {
401 } else if (val == TEMP_EXTCOMMERCIAL) {
413 #if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
414 enum boot_device get_boot_device(void)
416 struct bootrom_sw_info **p =
417 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
419 enum boot_device boot_dev = SD1_BOOT;
420 u8 boot_type = (*p)->boot_dev_type;
421 u8 boot_instance = (*p)->boot_dev_instance;
425 boot_dev = boot_instance + SD1_BOOT;
428 boot_dev = boot_instance + MMC1_BOOT;
431 boot_dev = NAND_BOOT;
434 boot_dev = QSPI_BOOT;
437 boot_dev = WEIM_NOR_BOOT;
439 case BOOT_TYPE_SPINOR:
440 boot_dev = SPI_NOR_BOOT;
455 #ifdef CONFIG_NXP_BOARD_REVISION
456 int nxp_board_rev(void)
459 * Get Board ID information from OCOTP_GP1[15:8]
464 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
465 struct fuse_bank *bank = &ocotp->bank[4];
466 struct fuse_bank4_regs *fuse =
467 (struct fuse_bank4_regs *)bank->fuse_regs;
469 return (readl(&fuse->gp1) >> 8 & 0x0F);
472 char nxp_board_rev_string(void)
474 const char *rev = "A";
476 return (*rev + nxp_board_rev() - 1);