1 // SPDX-License-Identifier: GPL-2.0+
4 * Sascha Hauer, Pengutronix
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
12 #include <linux/errno.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <imx_thermal.h>
20 #include <ipu_pixfmt.h>
24 #ifdef CONFIG_FSL_ESDHC_IMX
25 #include <fsl_esdhc_imx.h>
28 static u32 reset_cause = -1;
30 u32 get_imx_reset_cause(void)
32 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
34 if (reset_cause == -1) {
35 reset_cause = readl(&src_regs->srsr);
36 /* preserve the value for U-Boot proper */
37 #if !defined(CONFIG_SPL_BUILD)
38 writel(reset_cause, &src_regs->srsr);
45 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
46 static char *get_reset_cause(void)
48 switch (get_imx_reset_cause()) {
73 #elif defined(CONFIG_IMX8M)
85 return "unknown reset";
90 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
91 #if defined(CONFIG_MX53)
92 #define MEMCTL_BASE ESDCTL_BASE_ADDR
94 #define MEMCTL_BASE MMDC_P0_BASE_ADDR
96 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
97 static const unsigned char bank_lookup[] = {3, 2};
99 /* these MMDC registers are common to the IMX53 and IMX6 */
100 struct esd_mmdc_regs {
110 #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
111 #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
112 #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
113 #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
114 #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
117 * imx_ddr_size - return size in bytes of DRAM according MMDC config
118 * The MMDC MDCTL register holds the number of bits for row, col, and data
119 * width and the MMDC MDMISC register holds the number of banks. Combine
120 * all these bits to determine the meme size the MMDC has been configured for
122 unsigned imx_ddr_size(void)
124 struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
125 unsigned ctl = readl(&mem->ctl);
126 unsigned misc = readl(&mem->misc);
127 int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
129 bits += ESD_MMDC_CTL_GET_ROW(ctl);
130 bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
131 bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
132 bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
133 bits += ESD_MMDC_CTL_GET_CS1(ctl);
135 /* The MX6 can do only 3840 MiB of DRAM */
143 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
145 const char *get_imx_type(u32 imxtype)
149 return "8MQ"; /* Quad-core version of the imx8m */
151 return "7S"; /* Single-core version of the mx7 */
153 return "7D"; /* Dual-core version of the mx7 */
155 return "6QP"; /* Quad-Plus version of the mx6 */
157 return "6DP"; /* Dual-Plus version of the mx6 */
159 return "6Q"; /* Quad-core version of the mx6 */
161 return "6D"; /* Dual-core version of the mx6 */
163 return "6DL"; /* Dual Lite version of the mx6 */
164 case MXC_CPU_MX6SOLO:
165 return "6SOLO"; /* Solo version of the mx6 */
167 return "6SL"; /* Solo-Lite version of the mx6 */
169 return "6SLL"; /* SLL version of the mx6 */
171 return "6SX"; /* SoloX version of the mx6 */
173 return "6UL"; /* Ultra-Lite version of the mx6 */
175 return "6ULL"; /* ULL version of the mx6 */
185 int print_cpuinfo(void)
188 __maybe_unused u32 max_freq;
190 cpurev = get_cpu_rev();
192 #if defined(CONFIG_IMX_THERMAL)
193 struct udevice *thermal_dev;
194 int cpu_tmp, minc, maxc, ret;
196 printf("CPU: Freescale i.MX%s rev%d.%d",
197 get_imx_type((cpurev & 0xFF000) >> 12),
198 (cpurev & 0x000F0) >> 4,
199 (cpurev & 0x0000F) >> 0);
200 max_freq = get_cpu_speed_grade_hz();
201 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
202 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
204 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
205 mxc_get_clock(MXC_ARM_CLK) / 1000000);
208 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
209 get_imx_type((cpurev & 0xFF000) >> 12),
210 (cpurev & 0x000F0) >> 4,
211 (cpurev & 0x0000F) >> 0,
212 mxc_get_clock(MXC_ARM_CLK) / 1000000);
215 #if defined(CONFIG_IMX_THERMAL)
217 switch (get_cpu_temp_grade(&minc, &maxc)) {
218 case TEMP_AUTOMOTIVE:
219 puts("Automotive temperature grade ");
221 case TEMP_INDUSTRIAL:
222 puts("Industrial temperature grade ");
224 case TEMP_EXTCOMMERCIAL:
225 puts("Extended Commercial temperature grade ");
228 puts("Commercial temperature grade ");
231 printf("(%dC to %dC)", minc, maxc);
232 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
234 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
237 printf(" at %dC\n", cpu_tmp);
239 debug(" - invalid sensor data\n");
241 debug(" - invalid sensor device\n");
245 printf("Reset cause: %s\n", get_reset_cause());
250 int cpu_eth_init(bd_t *bis)
254 #if defined(CONFIG_FEC_MXC)
255 rc = fecmxc_initialize(bis);
261 #ifdef CONFIG_FSL_ESDHC_IMX
263 * Initializes on-chip MMC controllers.
264 * to override, implement board_mmc_init()
266 int cpu_mmc_init(bd_t *bis)
268 return fsl_esdhc_mmc_init(bis);
272 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
273 u32 get_ahb_clk(void)
275 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
278 reg = __raw_readl(&imx_ccm->cbcdr);
279 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
280 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
282 return get_periph_clk() / (ahb_podf + 1);
286 void arch_preboot_os(void)
288 #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
291 #if defined(CONFIG_SATA)
293 #if defined(CONFIG_MX6)
294 disable_sata_clock();
297 #if defined(CONFIG_VIDEO_IPUV3)
298 /* disable video before launching O/S */
301 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
307 void set_chipselect_size(int const cs_size)
310 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
311 reg = readl(&iomuxc_regs->gpr[1]);
315 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
318 case CS0_64M_CS1_64M:
319 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
322 case CS0_64M_CS1_32M_CS2_32M:
323 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
326 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
327 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
331 printf("Unknown chip select size: %d\n", cs_size);
335 writel(reg, &iomuxc_regs->gpr[1]);
339 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
341 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
342 * defines a 2-bit SPEED_GRADING
344 #define OCOTP_TESTER3_SPEED_SHIFT 8
346 OCOTP_TESTER3_SPEED_GRADE0,
347 OCOTP_TESTER3_SPEED_GRADE1,
348 OCOTP_TESTER3_SPEED_GRADE2,
349 OCOTP_TESTER3_SPEED_GRADE3,
352 u32 get_cpu_speed_grade_hz(void)
354 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
355 struct fuse_bank *bank = &ocotp->bank[1];
356 struct fuse_bank1_regs *fuse =
357 (struct fuse_bank1_regs *)bank->fuse_regs;
360 val = readl(&fuse->tester3);
361 val >>= OCOTP_TESTER3_SPEED_SHIFT;
365 case OCOTP_TESTER3_SPEED_GRADE0:
367 case OCOTP_TESTER3_SPEED_GRADE1:
368 return is_mx7() ? 500000000 : 1000000000;
369 case OCOTP_TESTER3_SPEED_GRADE2:
370 return is_mx7() ? 1000000000 : 1300000000;
371 case OCOTP_TESTER3_SPEED_GRADE3:
372 return is_mx7() ? 1200000000 : 1500000000;
379 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
380 * defines a 2-bit SPEED_GRADING
382 #define OCOTP_TESTER3_TEMP_SHIFT 6
384 u32 get_cpu_temp_grade(int *minc, int *maxc)
386 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
387 struct fuse_bank *bank = &ocotp->bank[1];
388 struct fuse_bank1_regs *fuse =
389 (struct fuse_bank1_regs *)bank->fuse_regs;
392 val = readl(&fuse->tester3);
393 val >>= OCOTP_TESTER3_TEMP_SHIFT;
397 if (val == TEMP_AUTOMOTIVE) {
400 } else if (val == TEMP_INDUSTRIAL) {
403 } else if (val == TEMP_EXTCOMMERCIAL) {
415 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
416 enum boot_device get_boot_device(void)
418 struct bootrom_sw_info **p =
419 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
421 enum boot_device boot_dev = SD1_BOOT;
422 u8 boot_type = (*p)->boot_dev_type;
423 u8 boot_instance = (*p)->boot_dev_instance;
427 boot_dev = boot_instance + SD1_BOOT;
430 boot_dev = boot_instance + MMC1_BOOT;
433 boot_dev = NAND_BOOT;
436 boot_dev = QSPI_BOOT;
439 boot_dev = WEIM_NOR_BOOT;
441 case BOOT_TYPE_SPINOR:
442 boot_dev = SPI_NOR_BOOT;
457 #ifdef CONFIG_NXP_BOARD_REVISION
458 int nxp_board_rev(void)
461 * Get Board ID information from OCOTP_GP1[15:8]
466 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
467 struct fuse_bank *bank = &ocotp->bank[4];
468 struct fuse_bank4_regs *fuse =
469 (struct fuse_bank4_regs *)bank->fuse_regs;
471 return (readl(&fuse->gp1) >> 8 & 0x0F);
474 char nxp_board_rev_string(void)
476 const char *rev = "A";
478 return (*rev + nxp_board_rev() - 1);