3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/errno.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/crm_regs.h>
19 #include <imx_thermal.h>
20 #include <ipu_pixfmt.h>
24 #ifdef CONFIG_FSL_ESDHC
25 #include <fsl_esdhc.h>
28 #if defined(CONFIG_DISPLAY_CPUINFO)
29 static u32 reset_cause = -1;
31 static char *get_reset_cause(void)
34 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
36 cause = readl(&src_regs->srsr);
37 writel(cause, &src_regs->srsr);
72 return "unknown reset";
76 u32 get_imx_reset_cause(void)
82 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
83 #if defined(CONFIG_MX53)
84 #define MEMCTL_BASE ESDCTL_BASE_ADDR
86 #define MEMCTL_BASE MMDC_P0_BASE_ADDR
88 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
89 static const unsigned char bank_lookup[] = {3, 2};
91 /* these MMDC registers are common to the IMX53 and IMX6 */
92 struct esd_mmdc_regs {
102 #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
103 #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
104 #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
105 #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
106 #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
109 * imx_ddr_size - return size in bytes of DRAM according MMDC config
110 * The MMDC MDCTL register holds the number of bits for row, col, and data
111 * width and the MMDC MDMISC register holds the number of banks. Combine
112 * all these bits to determine the meme size the MMDC has been configured for
114 unsigned imx_ddr_size(void)
116 struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
117 unsigned ctl = readl(&mem->ctl);
118 unsigned misc = readl(&mem->misc);
119 int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
121 bits += ESD_MMDC_CTL_GET_ROW(ctl);
122 bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
123 bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
124 bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
125 bits += ESD_MMDC_CTL_GET_CS1(ctl);
127 /* The MX6 can do only 3840 MiB of DRAM */
135 #if defined(CONFIG_DISPLAY_CPUINFO)
137 const char *get_imx_type(u32 imxtype)
141 return "7S"; /* Single-core version of the mx7 */
143 return "7D"; /* Dual-core version of the mx7 */
145 return "6QP"; /* Quad-Plus version of the mx6 */
147 return "6DP"; /* Dual-Plus version of the mx6 */
149 return "6Q"; /* Quad-core version of the mx6 */
151 return "6D"; /* Dual-core version of the mx6 */
153 return "6DL"; /* Dual Lite version of the mx6 */
154 case MXC_CPU_MX6SOLO:
155 return "6SOLO"; /* Solo version of the mx6 */
157 return "6SL"; /* Solo-Lite version of the mx6 */
159 return "6SLL"; /* SLL version of the mx6 */
161 return "6SX"; /* SoloX version of the mx6 */
163 return "6UL"; /* Ultra-Lite version of the mx6 */
165 return "6ULL"; /* ULL version of the mx6 */
175 int print_cpuinfo(void)
178 __maybe_unused u32 max_freq;
180 cpurev = get_cpu_rev();
182 #if defined(CONFIG_IMX_THERMAL)
183 struct udevice *thermal_dev;
184 int cpu_tmp, minc, maxc, ret;
186 printf("CPU: Freescale i.MX%s rev%d.%d",
187 get_imx_type((cpurev & 0xFF000) >> 12),
188 (cpurev & 0x000F0) >> 4,
189 (cpurev & 0x0000F) >> 0);
190 max_freq = get_cpu_speed_grade_hz();
191 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
192 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
194 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
195 mxc_get_clock(MXC_ARM_CLK) / 1000000);
198 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
199 get_imx_type((cpurev & 0xFF000) >> 12),
200 (cpurev & 0x000F0) >> 4,
201 (cpurev & 0x0000F) >> 0,
202 mxc_get_clock(MXC_ARM_CLK) / 1000000);
205 #if defined(CONFIG_IMX_THERMAL)
207 switch (get_cpu_temp_grade(&minc, &maxc)) {
208 case TEMP_AUTOMOTIVE:
209 puts("Automotive temperature grade ");
211 case TEMP_INDUSTRIAL:
212 puts("Industrial temperature grade ");
214 case TEMP_EXTCOMMERCIAL:
215 puts("Extended Commercial temperature grade ");
218 puts("Commercial temperature grade ");
221 printf("(%dC to %dC)", minc, maxc);
222 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
224 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
227 printf(" at %dC\n", cpu_tmp);
229 debug(" - invalid sensor data\n");
231 debug(" - invalid sensor device\n");
235 printf("Reset cause: %s\n", get_reset_cause());
240 int cpu_eth_init(bd_t *bis)
244 #if defined(CONFIG_FEC_MXC)
245 rc = fecmxc_initialize(bis);
251 #ifdef CONFIG_FSL_ESDHC
253 * Initializes on-chip MMC controllers.
254 * to override, implement board_mmc_init()
256 int cpu_mmc_init(bd_t *bis)
258 return fsl_esdhc_mmc_init(bis);
263 u32 get_ahb_clk(void)
265 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
268 reg = __raw_readl(&imx_ccm->cbcdr);
269 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
270 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
272 return get_periph_clk() / (ahb_podf + 1);
276 void arch_preboot_os(void)
278 #if defined(CONFIG_PCIE_IMX)
281 #if defined(CONFIG_SATA)
283 #if defined(CONFIG_MX6)
284 disable_sata_clock();
287 #if defined(CONFIG_VIDEO_IPUV3)
288 /* disable video before launching O/S */
291 #if defined(CONFIG_VIDEO_MXS)
296 void set_chipselect_size(int const cs_size)
299 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
300 reg = readl(&iomuxc_regs->gpr[1]);
304 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
307 case CS0_64M_CS1_64M:
308 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
311 case CS0_64M_CS1_32M_CS2_32M:
312 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
315 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
316 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
320 printf("Unknown chip select size: %d\n", cs_size);
324 writel(reg, &iomuxc_regs->gpr[1]);