1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
10 #include <asm/mach-imx/sys_proto.h>
12 static void enable_ca7_smp(void)
17 asm volatile ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(val));
21 /* Only set the SMP for Cortex A7 */
23 /* Read auxiliary control register */
24 asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
32 /* Write auxiliary control register */
33 asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
40 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
41 void enable_caches(void)
43 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
44 enum dcache_option option = DCACHE_WRITETHROUGH;
46 enum dcache_option option = DCACHE_WRITEBACK;
48 /* Avoid random hang when download by usb */
49 invalidate_dcache_all();
51 /* Set ACTLR.SMP bit for Cortex-A7 */
54 /* Enable D-cache. I-cache is already enabled in start.S */
57 /* Enable caching on OCRAM and ROM */
58 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
61 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
66 void enable_caches(void)
69 * Set ACTLR.SMP bit for Cortex-A7, even if the caches are
74 puts("WARNING: Caches not enabled\n");
78 #ifndef CONFIG_SYS_L2CACHE_OFF
79 #ifdef CONFIG_SYS_L2_PL310
80 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
81 void v7_outer_cache_enable(void)
83 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
84 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
85 unsigned int val, cache_id;
89 * Must disable the L2 before changing the latency parameters
90 * and auxiliary control register.
92 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
95 * Set bit 22 in the auxiliary control register. If this bit
96 * is cleared, PL310 treats Normal Shared Non-cacheable
97 * accesses as Cacheable no-allocate.
99 setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
101 if (is_mx6sl() || is_mx6sll()) {
102 val = readl(&iomux->gpr[11]);
103 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
104 /* L2 cache configured as OCRAM, reset it */
105 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
106 writel(val, &iomux->gpr[11]);
110 writel(0x132, &pl310->pl310_tag_latency_ctrl);
111 writel(0x132, &pl310->pl310_data_latency_ctrl);
113 val = readl(&pl310->pl310_prefetch_ctrl);
115 /* Turn on the L2 I/D prefetch, double linefill */
116 /* Set prefetch offset with any value except 23 as per errata 765569 */
120 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
121 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL/SX/DQP
123 * But according to ARM PL310 errata: 752271
124 * ID: 752271: Double linefill feature can cause data corruption
125 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
126 * Workaround: The only workaround to this erratum is to disable the
127 * double linefill feature. This is the default behavior.
129 cache_id = readl(&pl310->pl310_cache_id);
130 if (((cache_id & L2X0_CACHE_ID_PART_MASK) == L2X0_CACHE_ID_PART_L310)
131 && ((cache_id & L2X0_CACHE_ID_RTL_MASK) < L2X0_CACHE_ID_RTL_R3P2))
133 writel(val, &pl310->pl310_prefetch_ctrl);
135 val = readl(&pl310->pl310_power_ctrl);
136 val |= L2X0_DYNAMIC_CLK_GATING_EN;
137 val |= L2X0_STNDBY_MODE_EN;
138 writel(val, &pl310->pl310_power_ctrl);
140 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
143 void v7_outer_cache_disable(void)
145 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
147 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
149 #endif /* !CONFIG_SYS_L2_PL310 */
150 #endif /* !CONFIG_SYS_L2CACHE_OFF */